msdc cm12  d12
[TST] ==============================================
[TST] BEGIN: 1/1, No Stop(0)
[TST] ----------------------------------------------
[TST] Mode    : 2
[TST] Clock   : 48000 kHz
[TST] BusWidth: 4 bits
[TST] BurstSz : 64 bytes
[TST] BlkAddr : 40000h
[TST] BlkSize : 512bytes
[TST] TstBlks : 256
[TST] AutoCMD : 12(1), 23(0)
[TST] ----------------------------------------------
[SD0] Bus Width: 1
[SD0] SET_CLK(260kHz): SCLK(255kHz) MODE(0) DDR(0) DIV(47) DS(0) RS(0)
[SD0] Set read data timeout: 100000000ns 0clks -> 1 x 65536 cycles
[SD0] CMD(0): ARG(0x0), RAW(0x0), RSP(0)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(0): RSP(0)
[SD0] CMD(8): ARG(0x1aa), RAW(0x88), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(8): RSP(1) = 0x1aa AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] Switch error
	[CARD_STATUS] App Command
	[CARD_STATUS] 'Idle' State
[SD0] CMD(5): ARG(0x0), RAW(0x205), RSP(4)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x200)
[SD0] CMD(5): RSP(4) ERR(CMDTO) AUTO(0)
[SD0] CMD(5): ARG(0x0), RAW(0x205), RSP(4)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x200)
[SD0] CMD(5): RSP(4) ERR(CMDTO) AUTO(0)
[SD0] CMD(5): ARG(0x0), RAW(0x205), RSP(4)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x200)
[SD0] CMD(5): RSP(4) ERR(CMDTO) AUTO(0)
[SD0] CMD(5): ARG(0x0), RAW(0x205), RSP(4)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x200)
[SD0] CMD(5): RSP(4) ERR(CMDTO) AUTO(0)
[SD0] CMD(5): ARG(0x0), RAW(0x205), RSP(4)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x200)
[SD0] CMD(5): RSP(4) ERR(CMDTO) AUTO(0)
[SD0] CMD(5): ARG(0x0), RAW(0x205), RSP(4)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x200)
[SD0] CMD(5): RSP(4) ERR(CMDTO) AUTO(0)
[SD0] CMD(55): ARG(0x0), RAW(0xb7), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(55): RSP(1) = 0x120 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] App Command
	[CARD_STATUS] 'Idle' State
[SD0] CMD(41): ARG(0x0), RAW(0x1a9), RSP(3)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(41): RSP(3) = 0xff8000 AUTO(0)
	[OCR] 2.7-2.8 volt
	[OCR] 2.8-2.9 volt
	[OCR] 2.9-3.0 volt
	[OCR] 3.0-3.1 volt
	[OCR] 3.1-3.2 volt
	[OCR] 3.2-3.3 volt
	[OCR] 3.3-3.4 volt
	[OCR] 3.4-3.5 volt
	[OCR] 3.5-3.6 volt
	[OCR] Card Power Up Status (Busy)
[SD0] CMD(0): ARG(0x0), RAW(0x0), RSP(0)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(0): RSP(0)
[SD0] CMD(8): ARG(0x1aa), RAW(0x88), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(8): RSP(1) = 0x1aa AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] Switch error
	[CARD_STATUS] App Command
	[CARD_STATUS] 'Idle' State
[SD0] CMD(55): ARG(0x0), RAW(0xb7), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(55): RSP(1) = 0x120 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] App Command
	[CARD_STATUS] 'Idle' State
[SD0] CMD(41): ARG(0x51200000), RAW(0x1a9), RSP(3)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(41): RSP(3) = 0xff8000 AUTO(0)
	[OCR] 2.7-2.8 volt
	[OCR] 2.8-2.9 volt
	[OCR] 2.9-3.0 volt
	[OCR] 3.0-3.1 volt
	[OCR] 3.1-3.2 volt
	[OCR] 3.2-3.3 volt
	[OCR] 3.3-3.4 volt
	[OCR] 3.4-3.5 volt
	[OCR] 3.5-3.6 volt
	[OCR] Card Power Up Status (Busy)
[SD0] CMD(55): ARG(0x0), RAW(0xb7), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(55): RSP(1) = 0x120 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] App Command
	[CARD_STATUS] 'Idle' State
[SD0] CMD(41): ARG(0x51200000), RAW(0x1a9), RSP(3)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(41): RSP(3) = 0x80ff8000 AUTO(0)
	[OCR] 2.7-2.8 volt
	[OCR] 2.8-2.9 volt
	[OCR] 2.9-3.0 volt
	[OCR] 3.0-3.1 volt
	[OCR] 3.1-3.2 volt
	[OCR] 3.2-3.3 volt
	[OCR] 3.3-3.4 volt
	[OCR] 3.4-3.5 volt
	[OCR] 3.5-3.6 volt
	[OCR] Card Power Up Status (Idle)
[SD0] CMD(2): ARG(0x0), RAW(0x102), RSP(2)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(2): RSP(2) = 0x1b534d30 0x30303030 0x1011d000 0x1200b4c7
[SD0] CMD(3): ARG(0x0), RAW(0x83), RSP(6)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(3): RSP(6) = 0x20520 AUTO(0)
	[RCA] 0x2
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] App Command
	[CARD_STATUS] 'Ident' State
[SD0] CMD(9): ARG(0x20000), RAW(0x109), RSP(2)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(9): RSP(2) = 0x7fff32 0x5b5a83ba 0xf6dbdfff 0xe8000b5
[CSD] CSD v1.0
[CSD] TACC_NS: 80000000 ns, TACC_CLKS: 25500 clks
[CSD] Read Blk Len = 1024, Write Blk Len = 1024
[CSD] CMD Class:'basic' 'block read' 'block write' 'erase' 'lock card' 'app-spec' 'switch' 
[SD0] CMD(7): ARG(0x20000), RAW(0x387), RSP(8)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(7): RSP(8) = 0x700 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Stby' State
[SD0] Set read data timeout: 100000000ns 0clks -> 1 x 65536 cycles
[SD0] CMD(55): ARG(0x20000), RAW(0x800b7), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(55): RSP(1) = 0x920 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] App Command
	[CARD_STATUS] 'Tran' State
[SD0] CMD(51): ARG(0x0), RAW(0x808b3), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x1100)
[SD0]<CHECKME> Unexpected INT(0x1000)
[SD0] CMD(51): RSP(1) = 0x920 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] App Command
	[CARD_STATUS] 'Tran' State
[SD0] Read left bytes, RXFIFOCNT: 0, Left: 0/8
[SD0] SCR: 802502 0 (raw)
[SD0] SCR: 0 2258000 (ntohl)
[SD0] SD_SPEC(2) SD_SPEC3(1) SD_BUS_WIDTH=5
[SD0] SD_SECU(2) EX_SECU(0), CMD_SUPP(0): CMD23(0), CMD20(0)
[SD0] Set read data timeout: 100000000ns 0clks -> 1 x 65536 cycles
[SD0] CMD(6): ARG(0xfffff1), RAW(0x400886), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x1100)
[SD0]<CHECKME> Unexpected INT(0x1000)
[SD0] CMD(6): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Read 64 bytes, RXFIFOCNT: 0,  Left: 0/64
  [511-384] 1806400h 1800180h 1800180h 380h
  [383-256] 1h 0h 0h 0h
  [255-128] 0h 0h 0h 0h
  [127-0] 0h 0h 0h 0h
  [511-448] 0h 64h 80h 1h 80h 1h 80h 1h
  [447-384] 80h 1h 80h 1h 80h 3h 0h 0h
  [383-320] 1h 0h 0h 0h 0h 0h 0h 0h
  [319-256] 0h 0h 0h 0h 0h 0h 0h 0h
  [255-192] 0h 0h 0h 0h 0h 0h 0h 0h
  [191-128] 0h 0h 0h 0h 0h 0h 0h 0h
  [127-64] 0h 0h 0h 0h 0h 0h 0h 0h
  [63-0] 0h 0h 0h 0h 0h 0h 0h 0h
[SD0] Support: Default/SDR12
[SD0] Support: HS/SDR25
[SD0] Support: Type-B Drv
[SD0] Support: 200mA current limit
[SD0] Set read data timeout: 100000000ns 0clks -> 1 x 65536 cycles
[SD0] CMD(6): ARG(0x80fffff1), RAW(0x400886), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x1100)
[SD0]<CHECKME> Unexpected INT(0x1000)
[SD0] CMD(6): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Read 64 bytes, RXFIFOCNT: 0,  Left: 0/64
  [511-384] 1806400h 1800180h 1800180h 380h
  [383-256] 1h 0h 0h 0h
  [255-128] 0h 0h 0h 0h
  [127-0] 0h 0h 0h 0h
  [511-448] 0h 64h 80h 1h 80h 1h 80h 1h
  [447-384] 80h 1h 80h 1h 80h 3h 0h 0h
  [383-320] 1h 0h 0h 0h 0h 0h 0h 0h
  [319-256] 0h 0h 0h 0h 0h 0h 0h 0h
  [255-192] 0h 0h 0h 0h 0h 0h 0h 0h
  [191-128] 0h 0h 0h 0h 0h 0h 0h 0h
  [127-64] 0h 0h 0h 0h 0h 0h 0h 0h
  [63-0] 0h 0h 0h 0h 0h 0h 0h 0h
[SD0] Switch to HS mode!
[SD0] CMD(55): ARG(0x20000), RAW(0x4000b7), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(55): RSP(1) = 0x920 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] App Command
	[CARD_STATUS] 'Tran' State
[SD0] CMD(6): ARG(0x2), RAW(0x400086), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(6): RSP(1) = 0x920 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] App Command
	[CARD_STATUS] 'Tran' State
[SD0] Bus Width: 4
[SD0] CMD(16): ARG(0x200), RAW(0x400090), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(16): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] CMD(55): ARG(0x20000), RAW(0x20000b7), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(55): RSP(1) = 0x920 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] App Command
	[CARD_STATUS] 'Tran' State
[SD0] CMD(42): ARG(0x0), RAW(0x20000aa), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(42): RSP(1) = 0x920 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] App Command
	[CARD_STATUS] 'Tran' State
[SD0] Size: 1910 MB, Max.Speed: 50000 kHz, blklen(512), nblks(3911680), ro(0)
[SD0] Initialized
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] CMD(55): ARG(0x20000), RAW(0x20000b7), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(55): RSP(1) = 0x920 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] App Command
	[CARD_STATUS] 'Tran' State
[SD0] CMD(6): ARG(0x2), RAW(0x2000086), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(6): RSP(1) = 0x920 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] App Command
	[CARD_STATUS] 'Tran' State
[SD0] Bus Width: 4
[SD0] CMD(16): ARG(0x200), RAW(0x2000090), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(16): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] CMD(32): ARG(0x8000000), RAW(0x20000a0), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(32): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] CMD(33): ARG(0x8020000), RAW(0x20000a1), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(33): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] CMD(38): ARG(0x0), RAW(0x20003a6), RSP(8)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(38): RSP(8) = 0x800 AUTO(0)
	[CARD_STATUS] 'Tran' State
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[TST] 0x8000000 - 0x8020000 Erased
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write data 1 blks to 0x8000000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8000000), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1fc57c0
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8000200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8000200), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8000400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8000400), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8000600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8000600), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8000800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8000800), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8000a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8000a00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8000c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8000c00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8000e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8000e00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8001000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8001000), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8001200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8001200), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8001400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8001400), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8001600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8001600), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8001800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8001800), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8001a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8001a00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8001c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8001c00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8001e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8001e00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8002000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8002000), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8002200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8002200), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8002400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8002400), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8002600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8002600), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8002800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8002800), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8002a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8002a00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8002c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8002c00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8002e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8002e00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8003000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8003000), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8003200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8003200), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8003400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8003400), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8003600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8003600), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8003800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8003800), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8003a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8003a00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8003c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8003c00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8003e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8003e00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8004000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8004000), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8004200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8004200), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8004400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8004400), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8004600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8004600), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8004800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8004800), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8004a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8004a00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8004c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8004c00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8004e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8004e00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8005000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8005000), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8005200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8005200), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8005400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8005400), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8005600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8005600), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8005800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8005800), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8005a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8005a00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8005c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8005c00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8005e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8005e00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8006000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8006000), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8006200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8006200), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8006400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8006400), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8006600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8006600), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8006800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8006800), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8006a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8006a00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8006c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8006c00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8006e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8006e00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8007000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8007000), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8007200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8007200), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8007400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8007400), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8007600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8007600), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8007800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8007800), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8007a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8007a00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8007c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8007c00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8007e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8007e00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8008000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8008000), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8008200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8008200), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8008400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8008400), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8008600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8008600), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8008800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8008800), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8008a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8008a00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8008c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8008c00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8008e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8008e00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8009000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8009000), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8009200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8009200), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8009400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8009400), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8009600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8009600), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8009800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8009800), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8009a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8009a00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8009c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8009c00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8009e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8009e00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800a000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800a000), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800a200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800a200), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800a400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800a400), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800a600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800a600), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800a800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800a800), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800aa00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800aa00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800ac00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800ac00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800ae00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800ae00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800b000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800b000), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800b200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800b200), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800b400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800b400), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800b600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800b600), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800b800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800b800), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800ba00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800ba00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800bc00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800bc00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800be00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800be00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800c000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800c000), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800c200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800c200), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800c400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800c400), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800c600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800c600), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800c800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800c800), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800ca00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800ca00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800cc00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800cc00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800ce00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800ce00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800d000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800d000), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800d200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800d200), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800d400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800d400), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800d600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800d600), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800d800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800d800), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800da00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800da00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800dc00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800dc00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800de00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800de00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800e000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800e000), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800e200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800e200), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800e400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800e400), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800e600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800e600), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800e800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800e800), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800ea00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800ea00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800ec00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800ec00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800ee00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800ee00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800f000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800f000), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800f200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800f200), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800f400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800f400), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800f600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800f600), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800f800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800f800), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800fa00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800fa00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800fc00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800fc00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800fe00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800fe00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8010000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8010000), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8010200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8010200), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8010400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8010400), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8010600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8010600), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8010800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8010800), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8010a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8010a00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8010c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8010c00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8010e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8010e00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8011000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8011000), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8011200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8011200), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8011400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8011400), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8011600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8011600), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8011800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8011800), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8011a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8011a00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8011c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8011c00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8011e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8011e00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8012000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8012000), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8012200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8012200), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8012400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8012400), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8012600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8012600), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8012800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8012800), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8012a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8012a00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8012c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8012c00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8012e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8012e00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8013000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8013000), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8013200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8013200), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8013400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8013400), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8013600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8013600), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8013800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8013800), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8013a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8013a00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8013c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8013c00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8013e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8013e00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8014000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8014000), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8014200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8014200), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8014400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8014400), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8014600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8014600), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8014800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8014800), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8014a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8014a00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8014c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8014c00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8014e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8014e00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8015000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8015000), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8015200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8015200), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8015400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8015400), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8015600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8015600), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8015800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8015800), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8015a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8015a00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8015c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8015c00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8015e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8015e00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8016000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8016000), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8016200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8016200), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8016400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8016400), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8016600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8016600), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8016800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8016800), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8016a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8016a00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8016c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8016c00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8016e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8016e00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8017000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8017000), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8017200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8017200), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8017400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8017400), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8017600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8017600), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8017800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8017800), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8017a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8017a00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8017c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8017c00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8017e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8017e00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8018000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8018000), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8018200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8018200), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8018400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8018400), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8018600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8018600), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8018800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8018800), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8018a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8018a00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8018c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8018c00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8018e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8018e00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8019000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8019000), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8019200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8019200), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8019400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8019400), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8019600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8019600), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8019800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8019800), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8019a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8019a00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8019c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8019c00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8019e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8019e00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801a000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801a000), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801a200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801a200), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801a400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801a400), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801a600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801a600), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801a800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801a800), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801aa00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801aa00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801ac00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801ac00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801ae00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801ae00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801b000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801b000), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801b200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801b200), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801b400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801b400), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801b600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801b600), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801b800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801b800), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801ba00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801ba00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801bc00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801bc00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801be00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801be00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801c000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801c000), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801c200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801c200), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801c400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801c400), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801c600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801c600), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801c800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801c800), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801ca00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801ca00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801cc00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801cc00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801ce00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801ce00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801d000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801d000), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801d200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801d200), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801d400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801d400), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801d600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801d600), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801d800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801d800), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801da00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801da00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801dc00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801dc00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801de00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801de00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801e000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801e000), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801e200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801e200), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801e400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801e400), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801e600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801e600), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801e800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801e800), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801ea00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801ea00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801ec00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801ec00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801ee00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801ee00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801f000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801f000), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801f200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801f200), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801f400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801f400), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801f600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801f600), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801f800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801f800), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801fa00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801fa00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801fc00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801fc00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801fe00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801fe00), RAW(0x2002898), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] <PASS> TC0: test single block write
[SD0] Read data 1 blks from 0x8000000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8000000), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8000200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8000200), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8000400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8000400), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8000600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8000600), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8000800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8000800), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8000a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8000a00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8000c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8000c00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8000e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8000e00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8001000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8001000), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8001200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8001200), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8001400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8001400), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8001600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8001600), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8001800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8001800), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8001a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8001a00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8001c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8001c00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8001e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8001e00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8002000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8002000), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8002200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8002200), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8002400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8002400), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8002600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8002600), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8002800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8002800), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8002a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8002a00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8002c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8002c00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8002e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8002e00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8003000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8003000), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8003200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8003200), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8003400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8003400), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8003600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8003600), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8003800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8003800), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8003a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8003a00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8003c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8003c00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8003e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8003e00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8004000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8004000), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8004200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8004200), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8004400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8004400), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8004600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8004600), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8004800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8004800), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8004a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8004a00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8004c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8004c00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8004e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8004e00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8005000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8005000), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8005200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8005200), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8005400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8005400), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8005600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8005600), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8005800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8005800), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8005a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8005a00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8005c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8005c00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8005e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8005e00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8006000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8006000), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8006200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8006200), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8006400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8006400), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8006600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8006600), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8006800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8006800), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8006a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8006a00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8006c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8006c00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8006e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8006e00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8007000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8007000), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8007200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8007200), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8007400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8007400), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8007600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8007600), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8007800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8007800), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8007a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8007a00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8007c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8007c00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8007e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8007e00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8008000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8008000), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8008200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8008200), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8008400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8008400), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8008600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8008600), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8008800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8008800), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8008a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8008a00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8008c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8008c00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8008e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8008e00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8009000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8009000), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8009200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8009200), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8009400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8009400), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8009600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8009600), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8009800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8009800), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8009a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8009a00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8009c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8009c00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8009e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8009e00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800a000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800a000), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800a200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800a200), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800a400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800a400), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800a600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800a600), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800a800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800a800), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800aa00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800aa00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800ac00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800ac00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800ae00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800ae00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800b000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800b000), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800b200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800b200), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800b400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800b400), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800b600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800b600), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800b800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800b800), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800ba00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800ba00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800bc00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800bc00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800be00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800be00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800c000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800c000), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800c200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800c200), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800c400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800c400), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800c600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800c600), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800c800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800c800), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800ca00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800ca00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800cc00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800cc00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800ce00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800ce00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800d000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800d000), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800d200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800d200), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800d400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800d400), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800d600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800d600), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800d800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800d800), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800da00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800da00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800dc00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800dc00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800de00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800de00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800e000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800e000), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800e200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800e200), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800e400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800e400), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800e600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800e600), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800e800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800e800), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800ea00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800ea00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800ec00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800ec00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800ee00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800ee00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800f000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800f000), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800f200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800f200), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800f400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800f400), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800f600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800f600), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800f800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800f800), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800fa00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800fa00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800fc00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800fc00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800fe00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800fe00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8010000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8010000), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8010200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8010200), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8010400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8010400), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8010600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8010600), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8010800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8010800), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8010a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8010a00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8010c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8010c00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8010e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8010e00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8011000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8011000), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8011200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8011200), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8011400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8011400), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8011600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8011600), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8011800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8011800), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8011a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8011a00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8011c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8011c00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8011e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8011e00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8012000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8012000), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8012200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8012200), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8012400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8012400), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8012600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8012600), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8012800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8012800), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8012a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8012a00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8012c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8012c00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8012e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8012e00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8013000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8013000), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8013200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8013200), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8013400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8013400), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8013600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8013600), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8013800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8013800), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8013a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8013a00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8013c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8013c00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8013e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8013e00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8014000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8014000), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8014200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8014200), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8014400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8014400), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8014600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8014600), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8014800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8014800), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8014a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8014a00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8014c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8014c00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8014e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8014e00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8015000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8015000), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8015200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8015200), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8015400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8015400), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8015600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8015600), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8015800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8015800), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8015a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8015a00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8015c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8015c00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8015e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8015e00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8016000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8016000), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8016200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8016200), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8016400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8016400), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8016600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8016600), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8016800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8016800), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8016a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8016a00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8016c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8016c00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8016e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8016e00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8017000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8017000), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8017200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8017200), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8017400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8017400), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8017600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8017600), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8017800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8017800), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8017a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8017a00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8017c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8017c00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8017e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8017e00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8018000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8018000), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8018200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8018200), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8018400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8018400), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8018600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8018600), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8018800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8018800), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8018a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8018a00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8018c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8018c00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8018e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8018e00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8019000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8019000), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8019200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8019200), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8019400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8019400), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8019600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8019600), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8019800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8019800), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8019a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8019a00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8019c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8019c00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8019e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8019e00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801a000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801a000), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801a200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801a200), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801a400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801a400), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801a600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801a600), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801a800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801a800), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801aa00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801aa00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801ac00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801ac00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801ae00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801ae00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801b000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801b000), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801b200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801b200), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801b400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801b400), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801b600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801b600), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801b800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801b800), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801ba00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801ba00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801bc00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801bc00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801be00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801be00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801c000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801c000), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801c200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801c200), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801c400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801c400), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801c600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801c600), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801c800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801c800), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801ca00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801ca00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801cc00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801cc00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801ce00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801ce00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801d000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801d000), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801d200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801d200), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801d400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801d400), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801d600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801d600), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801d800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801d800), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801da00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801da00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801dc00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801dc00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801de00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801de00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801e000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801e000), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801e200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801e200), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801e400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801e400), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801e600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801e600), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801e800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801e800), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801ea00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801ea00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801ec00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801ec00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801ee00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801ee00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801f000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801f000), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801f200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801f200), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801f400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801f400), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801f600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801f600), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801f800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801f800), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801fa00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801fa00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801fc00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801fc00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801fe00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801fe00), RAW(0x2000891), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x2006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3100)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] <PASS> TC1: test single block read
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write data 64 blks to 0x8000000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(25): ARG(0x8000000), RAW(0x12003099), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x80006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(25): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 1
[SD0] INT(0x3008)
[SD0] DMA AUTO CMD Rdy, Resp(c00h)
	[CARD_STATUS] 'Rcv' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 32768 bytes (DONE)
[SD0] Write data 64 blks to 0x8008000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(25): ARG(0x8008000), RAW(0x12003099), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x80006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3108)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(25): RSP(1) = 0xc00 AUTO(1)
	[CARD_STATUS] 'Rcv' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 32768 bytes (DONE)
[SD0] Write data 64 blks to 0x8010000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(25): ARG(0x8010000), RAW(0x12003099), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x80006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3108)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(25): RSP(1) = 0xc00 AUTO(1)
	[CARD_STATUS] 'Rcv' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 32768 bytes (DONE)
[SD0] Write data 64 blks to 0x8018000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(25): ARG(0x8018000), RAW(0x12003099), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x80006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3108)
[SD0]<CHECKME> Unexpected INT(0x3000)
[SD0] CMD(25): RSP(1) = 0xc00 AUTO(1)
	[CARD_STATUS] 'Rcv' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3000)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 32768 bytes (DONE)
[SD0] <PASS> TC2: test multiple block write
[SD0] Read data 64 blks from 0x8000000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(18): ARG(0x8000000), RAW(0x12001092), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x80006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3188)
[SD0]<CHECKME> Unexpected INT(0x3080)
[SD0] CMD(18): RSP(1) = 0xb00 AUTO(1)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Data' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3080)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] DMA Stopped
[SD0] Read data 64 blks from 0x8008000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(18): ARG(0x8008000), RAW(0x12001092), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x80006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3188)
[SD0]<CHECKME> Unexpected INT(0x3080)
[SD0] CMD(18): RSP(1) = 0xb00 AUTO(1)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Data' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3080)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] DMA Stopped
[SD0] Read data 64 blks from 0x8010000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(18): ARG(0x8010000), RAW(0x12001092), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x80006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3188)
[SD0]<CHECKME> Unexpected INT(0x3080)
[SD0] CMD(18): RSP(1) = 0xb00 AUTO(1)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Data' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3080)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] DMA Stopped
[SD0] Read data 64 blks from 0x8018000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(18): ARG(0x8018000), RAW(0x12001092), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x80006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3188)
[SD0]<CHECKME> Unexpected INT(0x3080)
[SD0] CMD(18): RSP(1) = 0xb00 AUTO(1)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Data' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3080)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] DMA Stopped
[SD0] <PASS> TC3: test multiple block read
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x180)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write data 64 blks to 0x8000000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(25): ARG(0x8000000), RAW(0x12003099), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x80006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x180)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] CMD(25): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3088)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] DMA AUTO CMD Rdy, Resp(c00h)
	[CARD_STATUS] 'Rcv' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x180)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 32768 bytes (DONE)
[SD0] Read data 64 blks from 0x8000000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(18): ARG(0x8000000), RAW(0x12001092), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x80006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3188)
[SD0]<CHECKME> Unexpected INT(0x3080)
[SD0] CMD(18): RSP(1) = 0xb00 AUTO(1)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Data' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3080)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] DMA Stopped
[SD0] Write data 64 blks to 0x8008000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(25): ARG(0x8008000), RAW(0x12003099), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x80006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3188)
[SD0]<CHECKME> Unexpected INT(0x3080)
[SD0] CMD(25): RSP(1) = 0xc00 AUTO(1)
	[CARD_STATUS] 'Rcv' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3080)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x180)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 32768 bytes (DONE)
[SD0] Read data 64 blks from 0x8008000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(18): ARG(0x8008000), RAW(0x12001092), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x80006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3188)
[SD0]<CHECKME> Unexpected INT(0x3080)
[SD0] CMD(18): RSP(1) = 0xb00 AUTO(1)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Data' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3080)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] DMA Stopped
[SD0] Write data 64 blks to 0x8010000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(25): ARG(0x8010000), RAW(0x12003099), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x80006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x180)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] CMD(25): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 1
[SD0] INT(0x3088)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] DMA AUTO CMD Rdy, Resp(c00h)
	[CARD_STATUS] 'Rcv' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x180)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 32768 bytes (DONE)
[SD0] Read data 64 blks from 0x8010000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(18): ARG(0x8010000), RAW(0x12001092), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x80006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3188)
[SD0]<CHECKME> Unexpected INT(0x3080)
[SD0] CMD(18): RSP(1) = 0xb00 AUTO(1)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Data' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3080)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] DMA Stopped
[SD0] Write data 64 blks to 0x8018000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(25): ARG(0x8018000), RAW(0x12003099), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x80006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3188)
[SD0]<CHECKME> Unexpected INT(0x3080)
[SD0] CMD(25): RSP(1) = 0xc00 AUTO(1)
	[CARD_STATUS] 'Rcv' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3080)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x180)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 32768 bytes (DONE)
[SD0] Read data 64 blks from 0x8018000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(18): ARG(0x8018000), RAW(0x12001092), RSP(1)
[SD0] DMA_SA   = 0x1f7c7f4
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x80006400
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3188)
[SD0]<CHECKME> Unexpected INT(0x3080)
[SD0] CMD(18): RSP(1) = 0xb00 AUTO(1)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Data' State
[SD0] DMA Curr Addr: 0x1f7c7f4, Active: 0
[SD0] INT(0x3080)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] DMA Stopped
[SD0] <PASS> TC4: test multiple block interleave write-read
[TST] ----------------------------------------------
[TST] Report -  Auto CMD12 Test 
[TST] ----------------------------------------------
[TST] ----------------------------------------------
[TST] Test Result: TOTAL(1/1), PASS(1), FAIL(0) 
[TST] ----------------------------------------------
[TST] ==============================================
[TST] BEGIN: 1/1, No Stop(0)
[TST] ----------------------------------------------
[TST] Mode    : 3
[TST] Clock   : 48000 kHz
[TST] BusWidth: 4 bits
[TST] BurstSz : 64 bytes
[TST] BlkAddr : 40000h
[TST] BlkSize : 512bytes
[TST] TstBlks : 256
[TST] AutoCMD : 12(1), 23(0)
[TST] ----------------------------------------------
[SD0] Bus Width: 1
[SD0] SET_CLK(260kHz): SCLK(255kHz) MODE(0) DDR(0) DIV(47) DS(0) RS(0)
[SD0] Set read data timeout: 100000000ns 0clks -> 1 x 65536 cycles
[SD0] CMD(0): ARG(0x0), RAW(0x0), RSP(0)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(0): RSP(0)
[SD0] CMD(8): ARG(0x1aa), RAW(0x88), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(8): RSP(1) = 0x1aa AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] Switch error
	[CARD_STATUS] App Command
	[CARD_STATUS] 'Idle' State
[SD0] CMD(5): ARG(0x0), RAW(0x205), RSP(4)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x200)
[SD0] CMD(5): RSP(4) ERR(CMDTO) AUTO(0)
[SD0] CMD(5): ARG(0x0), RAW(0x205), RSP(4)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x200)
[SD0] CMD(5): RSP(4) ERR(CMDTO) AUTO(0)
[SD0] CMD(5): ARG(0x0), RAW(0x205), RSP(4)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x200)
[SD0] CMD(5): RSP(4) ERR(CMDTO) AUTO(0)
[SD0] CMD(5): ARG(0x0), RAW(0x205), RSP(4)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x200)
[SD0] CMD(5): RSP(4) ERR(CMDTO) AUTO(0)
[SD0] CMD(5): ARG(0x0), RAW(0x205), RSP(4)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x200)
[SD0] CMD(5): RSP(4) ERR(CMDTO) AUTO(0)
[SD0] CMD(5): ARG(0x0), RAW(0x205), RSP(4)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x200)
[SD0] CMD(5): RSP(4) ERR(CMDTO) AUTO(0)
[SD0] CMD(55): ARG(0x0), RAW(0xb7), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(55): RSP(1) = 0x120 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] App Command
	[CARD_STATUS] 'Idle' State
[SD0] CMD(41): ARG(0x0), RAW(0x1a9), RSP(3)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(41): RSP(3) = 0xff8000 AUTO(0)
	[OCR] 2.7-2.8 volt
	[OCR] 2.8-2.9 volt
	[OCR] 2.9-3.0 volt
	[OCR] 3.0-3.1 volt
	[OCR] 3.1-3.2 volt
	[OCR] 3.2-3.3 volt
	[OCR] 3.3-3.4 volt
	[OCR] 3.4-3.5 volt
	[OCR] 3.5-3.6 volt
	[OCR] Card Power Up Status (Busy)
[SD0] CMD(0): ARG(0x0), RAW(0x0), RSP(0)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(0): RSP(0)
[SD0] CMD(8): ARG(0x1aa), RAW(0x88), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(8): RSP(1) = 0x1aa AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] Switch error
	[CARD_STATUS] App Command
	[CARD_STATUS] 'Idle' State
[SD0] CMD(55): ARG(0x0), RAW(0xb7), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(55): RSP(1) = 0x120 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] App Command
	[CARD_STATUS] 'Idle' State
[SD0] CMD(41): ARG(0x51200000), RAW(0x1a9), RSP(3)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(41): RSP(3) = 0xff8000 AUTO(0)
	[OCR] 2.7-2.8 volt
	[OCR] 2.8-2.9 volt
	[OCR] 2.9-3.0 volt
	[OCR] 3.0-3.1 volt
	[OCR] 3.1-3.2 volt
	[OCR] 3.2-3.3 volt
	[OCR] 3.3-3.4 volt
	[OCR] 3.4-3.5 volt
	[OCR] 3.5-3.6 volt
	[OCR] Card Power Up Status (Busy)
[SD0] CMD(55): ARG(0x0), RAW(0xb7), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(55): RSP(1) = 0x120 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] App Command
	[CARD_STATUS] 'Idle' State
[SD0] CMD(41): ARG(0x51200000), RAW(0x1a9), RSP(3)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(41): RSP(3) = 0x80ff8000 AUTO(0)
	[OCR] 2.7-2.8 volt
	[OCR] 2.8-2.9 volt
	[OCR] 2.9-3.0 volt
	[OCR] 3.0-3.1 volt
	[OCR] 3.1-3.2 volt
	[OCR] 3.2-3.3 volt
	[OCR] 3.3-3.4 volt
	[OCR] 3.4-3.5 volt
	[OCR] 3.5-3.6 volt
	[OCR] Card Power Up Status (Idle)
[SD0] CMD(2): ARG(0x0), RAW(0x102), RSP(2)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(2): RSP(2) = 0x1b534d30 0x30303030 0x1011d000 0x1200b4c7
[SD0] CMD(3): ARG(0x0), RAW(0x83), RSP(6)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(3): RSP(6) = 0x20520 AUTO(0)
	[RCA] 0x2
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] App Command
	[CARD_STATUS] 'Ident' State
[SD0] CMD(9): ARG(0x20000), RAW(0x109), RSP(2)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(9): RSP(2) = 0x7fff32 0x5b5a83ba 0xf6dbdfff 0xe8000b5
[CSD] CSD v1.0
[CSD] TACC_NS: 80000000 ns, TACC_CLKS: 25500 clks
[CSD] Read Blk Len = 1024, Write Blk Len = 1024
[CSD] CMD Class:'basic' 'block read' 'block write' 'erase' 'lock card' 'app-spec' 'switch' 
[SD0] CMD(7): ARG(0x20000), RAW(0x387), RSP(8)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(7): RSP(8) = 0x700 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Stby' State
[SD0] Set read data timeout: 100000000ns 0clks -> 1 x 65536 cycles
[SD0] CMD(55): ARG(0x20000), RAW(0x800b7), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(55): RSP(1) = 0x920 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] App Command
	[CARD_STATUS] 'Tran' State
[SD0] CMD(51): ARG(0x0), RAW(0x808b3), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x1100)
[SD0]<CHECKME> Unexpected INT(0x1000)
[SD0] CMD(51): RSP(1) = 0x920 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] App Command
	[CARD_STATUS] 'Tran' State
[SD0] Read left bytes, RXFIFOCNT: 0, Left: 0/8
[SD0] SCR: 802502 0 (raw)
[SD0] SCR: 0 2258000 (ntohl)
[SD0] SD_SPEC(2) SD_SPEC3(1) SD_BUS_WIDTH=5
[SD0] SD_SECU(2) EX_SECU(0), CMD_SUPP(0): CMD23(0), CMD20(0)
[SD0] Set read data timeout: 100000000ns 0clks -> 1 x 65536 cycles
[SD0] CMD(6): ARG(0xfffff1), RAW(0x400886), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x1100)
[SD0]<CHECKME> Unexpected INT(0x1000)
[SD0] CMD(6): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Read 64 bytes, RXFIFOCNT: 0,  Left: 0/64
  [511-384] 1806400h 1800180h 1800180h 380h
  [383-256] 1h 0h 0h 0h
  [255-128] 0h 0h 0h 0h
  [127-0] 0h 0h 0h 0h
  [511-448] 0h 64h 80h 1h 80h 1h 80h 1h
  [447-384] 80h 1h 80h 1h 80h 3h 0h 0h
  [383-320] 1h 0h 0h 0h 0h 0h 0h 0h
  [319-256] 0h 0h 0h 0h 0h 0h 0h 0h
  [255-192] 0h 0h 0h 0h 0h 0h 0h 0h
  [191-128] 0h 0h 0h 0h 0h 0h 0h 0h
  [127-64] 0h 0h 0h 0h 0h 0h 0h 0h
  [63-0] 0h 0h 0h 0h 0h 0h 0h 0h
[SD0] Support: Default/SDR12
[SD0] Support: HS/SDR25
[SD0] Support: Type-B Drv
[SD0] Support: 200mA current limit
[SD0] Set read data timeout: 100000000ns 0clks -> 1 x 65536 cycles
[SD0] CMD(6): ARG(0x80fffff1), RAW(0x400886), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x1100)
[SD0]<CHECKME> Unexpected INT(0x1000)
[SD0] CMD(6): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Read 64 bytes, RXFIFOCNT: 0,  Left: 0/64
  [511-384] 1806400h 1800180h 1800180h 380h
  [383-256] 1h 0h 0h 0h
  [255-128] 0h 0h 0h 0h
  [127-0] 0h 0h 0h 0h
  [511-448] 0h 64h 80h 1h 80h 1h 80h 1h
  [447-384] 80h 1h 80h 1h 80h 3h 0h 0h
  [383-320] 1h 0h 0h 0h 0h 0h 0h 0h
  [319-256] 0h 0h 0h 0h 0h 0h 0h 0h
  [255-192] 0h 0h 0h 0h 0h 0h 0h 0h
  [191-128] 0h 0h 0h 0h 0h 0h 0h 0h
  [127-64] 0h 0h 0h 0h 0h 0h 0h 0h
  [63-0] 0h 0h 0h 0h 0h 0h 0h 0h
[SD0] Switch to HS mode!
[SD0] CMD(55): ARG(0x20000), RAW(0x4000b7), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(55): RSP(1) = 0x920 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] App Command
	[CARD_STATUS] 'Tran' State
[SD0] CMD(6): ARG(0x2), RAW(0x400086), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(6): RSP(1) = 0x920 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] App Command
	[CARD_STATUS] 'Tran' State
[SD0] Bus Width: 4
[SD0] CMD(16): ARG(0x200), RAW(0x400090), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(16): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] CMD(55): ARG(0x20000), RAW(0x20000b7), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(55): RSP(1) = 0x920 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] App Command
	[CARD_STATUS] 'Tran' State
[SD0] CMD(42): ARG(0x0), RAW(0x20000aa), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(42): RSP(1) = 0x920 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] App Command
	[CARD_STATUS] 'Tran' State
[SD0] Size: 1910 MB, Max.Speed: 50000 kHz, blklen(512), nblks(3911680), ro(0)
[SD0] Initialized
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] CMD(55): ARG(0x20000), RAW(0x20000b7), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(55): RSP(1) = 0x920 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] App Command
	[CARD_STATUS] 'Tran' State
[SD0] CMD(6): ARG(0x2), RAW(0x2000086), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(6): RSP(1) = 0x920 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] App Command
	[CARD_STATUS] 'Tran' State
[SD0] Bus Width: 4
[SD0] CMD(16): ARG(0x200), RAW(0x2000090), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(16): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] CMD(32): ARG(0x8000000), RAW(0x20000a0), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(32): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] CMD(33): ARG(0x8020000), RAW(0x20000a1), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(33): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] CMD(38): ARG(0x0), RAW(0x20003a6), RSP(8)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(38): RSP(8) = 0x800 AUTO(0)
	[CARD_STATUS] 'Tran' State
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[TST] 0x8000000 - 0x8020000 Erased
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write data 1 blks to 0x8000000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8000000), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1f7c7f4
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8000200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8000200), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8000400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8000400), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8000600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8000600), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8000800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8000800), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8000a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8000a00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8000c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8000c00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8000e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8000e00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8001000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8001000), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8001200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8001200), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8001400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8001400), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8001600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8001600), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8001800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8001800), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8001a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8001a00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8001c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8001c00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8001e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8001e00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8002000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8002000), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8002200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8002200), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8002400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8002400), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8002600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8002600), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8002800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8002800), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8002a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8002a00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8002c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8002c00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8002e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8002e00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8003000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8003000), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8003200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8003200), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8003400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8003400), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8003600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8003600), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8003800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8003800), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8003a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8003a00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8003c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8003c00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8003e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8003e00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8004000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8004000), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8004200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8004200), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8004400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8004400), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8004600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8004600), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8004800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8004800), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8004a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8004a00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8004c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8004c00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8004e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8004e00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8005000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8005000), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8005200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8005200), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8005400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8005400), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8005600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8005600), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8005800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8005800), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8005a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8005a00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8005c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8005c00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8005e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8005e00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8006000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8006000), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8006200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8006200), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8006400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8006400), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8006600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8006600), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8006800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8006800), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8006a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8006a00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8006c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8006c00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8006e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8006e00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8007000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8007000), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8007200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8007200), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8007400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8007400), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8007600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8007600), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8007800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8007800), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8007a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8007a00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8007c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8007c00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8007e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8007e00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8008000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8008000), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8008200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8008200), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8008400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8008400), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8008600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8008600), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8008800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8008800), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8008a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8008a00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8008c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8008c00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8008e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8008e00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8009000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8009000), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8009200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8009200), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8009400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8009400), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8009600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8009600), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8009800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8009800), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8009a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8009a00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8009c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8009c00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8009e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8009e00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800a000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800a000), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800a200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800a200), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800a400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800a400), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800a600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800a600), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800a800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800a800), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800aa00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800aa00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800ac00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800ac00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800ae00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800ae00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800b000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800b000), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800b200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800b200), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800b400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800b400), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800b600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800b600), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800b800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800b800), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800ba00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800ba00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800bc00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800bc00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800be00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800be00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800c000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800c000), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800c200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800c200), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800c400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800c400), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800c600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800c600), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800c800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800c800), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800ca00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800ca00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800cc00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800cc00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800ce00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800ce00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800d000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800d000), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800d200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800d200), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800d400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800d400), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800d600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800d600), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800d800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800d800), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800da00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800da00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800dc00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800dc00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800de00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800de00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800e000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800e000), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800e200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800e200), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800e400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800e400), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800e600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800e600), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800e800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800e800), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800ea00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800ea00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800ec00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800ec00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800ee00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800ee00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800f000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800f000), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800f200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800f200), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800f400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800f400), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800f600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800f600), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800f800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800f800), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800fa00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800fa00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800fc00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800fc00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800fe00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x800fe00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8010000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8010000), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8010200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8010200), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8010400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8010400), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8010600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8010600), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8010800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8010800), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8010a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8010a00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8010c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8010c00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8010e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8010e00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8011000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8011000), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8011200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8011200), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8011400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8011400), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8011600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8011600), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8011800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8011800), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8011a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8011a00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8011c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8011c00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8011e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8011e00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8012000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8012000), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8012200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8012200), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8012400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8012400), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8012600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8012600), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8012800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8012800), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8012a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8012a00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8012c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8012c00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8012e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8012e00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8013000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8013000), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8013200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8013200), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8013400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8013400), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8013600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8013600), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8013800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8013800), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8013a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8013a00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8013c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8013c00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8013e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8013e00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8014000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8014000), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8014200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8014200), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8014400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8014400), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8014600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8014600), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8014800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8014800), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8014a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8014a00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8014c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8014c00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8014e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8014e00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8015000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8015000), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8015200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8015200), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8015400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8015400), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8015600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8015600), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8015800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8015800), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8015a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8015a00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8015c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8015c00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8015e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8015e00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8016000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8016000), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8016200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8016200), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8016400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8016400), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8016600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8016600), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8016800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8016800), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8016a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8016a00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8016c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8016c00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8016e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8016e00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8017000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8017000), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8017200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8017200), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8017400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8017400), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8017600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8017600), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8017800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8017800), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8017a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8017a00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8017c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8017c00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8017e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8017e00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8018000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8018000), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8018200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8018200), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8018400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8018400), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8018600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8018600), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8018800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8018800), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8018a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8018a00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8018c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8018c00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8018e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8018e00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8019000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8019000), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8019200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8019200), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8019400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8019400), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8019600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8019600), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8019800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8019800), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8019a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8019a00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8019c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8019c00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8019e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x8019e00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801a000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801a000), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801a200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801a200), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801a400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801a400), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801a600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801a600), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801a800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801a800), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801aa00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801aa00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801ac00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801ac00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801ae00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801ae00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801b000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801b000), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801b200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801b200), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801b400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801b400), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801b600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801b600), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801b800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801b800), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801ba00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801ba00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801bc00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801bc00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801be00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801be00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801c000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801c000), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801c200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801c200), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801c400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801c400), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801c600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801c600), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801c800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801c800), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801ca00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801ca00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801cc00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801cc00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801ce00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801ce00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801d000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801d000), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801d200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801d200), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801d400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801d400), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801d600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801d600), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801d800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801d800), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801da00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801da00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801dc00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801dc00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801de00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801de00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801e000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801e000), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801e200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801e200), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801e400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801e400), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801e600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801e600), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801e800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801e800), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801ea00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801ea00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801ec00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801ec00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801ee00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801ee00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801f000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801f000), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801f200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801f200), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801f400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801f400), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801f600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801f600), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801f800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801f800), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801fa00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801fa00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801fc00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801fc00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801fe00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(24): ARG(0x801fe00), RAW(0x2002898), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(24): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] <PASS> TC0: test single block write
[SD0] Read data 1 blks from 0x8000000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8000000), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8000200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8000200), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8000400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8000400), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8000600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8000600), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8000800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8000800), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8000a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8000a00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8000c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8000c00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8000e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8000e00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8001000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8001000), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8001200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8001200), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8001400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8001400), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8001600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8001600), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8001800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8001800), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8001a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8001a00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8001c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8001c00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8001e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8001e00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8002000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8002000), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8002200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8002200), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8002400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8002400), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8002600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8002600), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8002800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8002800), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8002a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8002a00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8002c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8002c00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8002e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8002e00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8003000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8003000), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8003200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8003200), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8003400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8003400), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8003600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8003600), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8003800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8003800), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8003a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8003a00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8003c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8003c00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8003e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8003e00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8004000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8004000), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8004200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8004200), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8004400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8004400), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8004600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8004600), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8004800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8004800), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8004a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8004a00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8004c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8004c00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8004e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8004e00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8005000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8005000), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8005200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8005200), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8005400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8005400), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8005600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8005600), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8005800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8005800), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8005a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8005a00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8005c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8005c00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8005e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8005e00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8006000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8006000), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8006200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8006200), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8006400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8006400), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8006600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8006600), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8006800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8006800), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8006a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8006a00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8006c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8006c00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8006e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8006e00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8007000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8007000), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8007200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8007200), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8007400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8007400), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8007600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8007600), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8007800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8007800), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8007a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8007a00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8007c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8007c00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8007e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8007e00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8008000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8008000), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8008200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8008200), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8008400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8008400), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8008600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8008600), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8008800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8008800), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8008a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8008a00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8008c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8008c00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8008e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8008e00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8009000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8009000), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8009200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8009200), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8009400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8009400), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8009600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8009600), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8009800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8009800), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8009a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8009a00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8009c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8009c00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8009e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8009e00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800a000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800a000), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800a200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800a200), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800a400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800a400), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800a600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800a600), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800a800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800a800), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800aa00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800aa00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800ac00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800ac00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800ae00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800ae00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800b000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800b000), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800b200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800b200), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800b400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800b400), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800b600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800b600), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800b800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800b800), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800ba00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800ba00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800bc00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800bc00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800be00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800be00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800c000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800c000), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800c200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800c200), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800c400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800c400), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800c600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800c600), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800c800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800c800), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800ca00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800ca00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800cc00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800cc00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800ce00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800ce00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800d000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800d000), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800d200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800d200), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800d400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800d400), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800d600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800d600), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800d800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800d800), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800da00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800da00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800dc00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800dc00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800de00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800de00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800e000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800e000), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800e200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800e200), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800e400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800e400), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800e600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800e600), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800e800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800e800), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800ea00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800ea00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800ec00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800ec00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800ee00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800ee00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800f000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800f000), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800f200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800f200), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800f400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800f400), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800f600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800f600), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800f800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800f800), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800fa00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800fa00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800fc00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800fc00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800fe00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x800fe00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8010000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8010000), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8010200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8010200), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8010400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8010400), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8010600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8010600), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8010800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8010800), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8010a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8010a00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8010c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8010c00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8010e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8010e00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8011000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8011000), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8011200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8011200), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8011400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8011400), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8011600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8011600), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8011800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8011800), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8011a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8011a00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8011c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8011c00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8011e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8011e00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8012000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8012000), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8012200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8012200), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8012400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8012400), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8012600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8012600), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8012800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8012800), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8012a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8012a00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8012c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8012c00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8012e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8012e00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8013000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8013000), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8013200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8013200), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8013400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8013400), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8013600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8013600), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8013800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8013800), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8013a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8013a00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8013c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8013c00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8013e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8013e00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8014000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8014000), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8014200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8014200), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8014400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8014400), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8014600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8014600), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8014800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8014800), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8014a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8014a00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8014c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8014c00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8014e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8014e00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8015000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8015000), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8015200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8015200), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8015400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8015400), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8015600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8015600), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8015800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8015800), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8015a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8015a00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8015c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8015c00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8015e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8015e00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8016000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8016000), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8016200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8016200), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8016400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8016400), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8016600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8016600), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8016800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8016800), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8016a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8016a00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8016c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8016c00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8016e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8016e00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8017000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8017000), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8017200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8017200), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8017400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8017400), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8017600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8017600), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8017800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8017800), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8017a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8017a00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8017c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8017c00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8017e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8017e00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8018000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8018000), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8018200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8018200), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8018400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8018400), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8018600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8018600), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8018800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8018800), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8018a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8018a00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8018c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8018c00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8018e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8018e00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8019000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8019000), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8019200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8019200), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8019400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8019400), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8019600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8019600), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8019800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8019800), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8019a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8019a00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8019c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8019c00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8019e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x8019e00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801a000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801a000), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801a200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801a200), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801a400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801a400), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801a600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801a600), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801a800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801a800), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801aa00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801aa00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801ac00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801ac00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801ae00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801ae00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801b000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801b000), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801b200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801b200), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801b400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801b400), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801b600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801b600), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801b800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801b800), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801ba00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801ba00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801bc00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801bc00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801be00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801be00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801c000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801c000), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801c200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801c200), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801c400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801c400), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801c600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801c600), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801c800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801c800), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801ca00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801ca00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801cc00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801cc00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801ce00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801ce00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801d000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801d000), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801d200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801d200), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801d400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801d400), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801d600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801d600), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801d800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801d800), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801da00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801da00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801dc00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801dc00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801de00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801de00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801e000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801e000), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801e200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801e200), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801e400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801e400), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801e600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801e600), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801e800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801e800), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801ea00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801ea00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801ec00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801ec00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801ee00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801ee00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801f000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801f000), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801f200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801f200), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801f400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801f400), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801f600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801f600), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801f800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801f800), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801fa00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801fa00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801fc00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801fc00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801fe00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(17): ARG(0x801fe00), RAW(0x2000891), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3140)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(17): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] <PASS> TC1: test single block read
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write data 64 blks to 0x8000000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(25): ARG(0x8000000), RAW(0x12003099), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): a700h 1fd3760h 1f7c7f4h 1000h
[SD0] BD[1](0x1fd3760h): 8700h 1fd3770h 1f7d7f4h 1000h
[SD0] BD[2](0x1fd3770h): 6700h 1fd3780h 1f7e7f4h 1000h
[SD0] BD[3](0x1fd3780h): 4700h 1fd3790h 1f7f7f4h 1000h
[SD0] BD[4](0x1fd3790h): 2600h 1fd37a0h 1f807f4h 1000h
[SD0] BD[5](0x1fd37a0h): 600h 1fd37b0h 1f817f4h 1000h
[SD0] BD[6](0x1fd37b0h): e600h 1fd37c0h 1f827f4h 1000h
[SD0] BD[7](0x1fd37c0h): ca01h 0h 1f837f4h 1000h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(25): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc5750, Active: 1
[SD0] INT(0x40)
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3008)
[SD0] DMA AUTO CMD Rdy, Resp(c00h)
	[CARD_STATUS] 'Rcv' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 32768 bytes (DONE)
[SD0] Write data 64 blks to 0x8008000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(25): ARG(0x8008000), RAW(0x12003099), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): a700h 1fd3760h 1f7c7f4h 1000h
[SD0] BD[1](0x1fd3760h): 8700h 1fd3770h 1f7d7f4h 1000h
[SD0] BD[2](0x1fd3770h): 6700h 1fd3780h 1f7e7f4h 1000h
[SD0] BD[3](0x1fd3780h): 4700h 1fd3790h 1f7f7f4h 1000h
[SD0] BD[4](0x1fd3790h): 2600h 1fd37a0h 1f807f4h 1000h
[SD0] BD[5](0x1fd37a0h): 600h 1fd37b0h 1f817f4h 1000h
[SD0] BD[6](0x1fd37b0h): e600h 1fd37c0h 1f827f4h 1000h
[SD0] BD[7](0x1fd37c0h): ca01h 0h 1f837f4h 1000h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3148)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(25): RSP(1) = 0xc00 AUTO(1)
	[CARD_STATUS] 'Rcv' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 32768 bytes (DONE)
[SD0] Write data 64 blks to 0x8010000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(25): ARG(0x8010000), RAW(0x12003099), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): a700h 1fd3760h 1f7c7f4h 1000h
[SD0] BD[1](0x1fd3760h): 8700h 1fd3770h 1f7d7f4h 1000h
[SD0] BD[2](0x1fd3770h): 6700h 1fd3780h 1f7e7f4h 1000h
[SD0] BD[3](0x1fd3780h): 4700h 1fd3790h 1f7f7f4h 1000h
[SD0] BD[4](0x1fd3790h): 2600h 1fd37a0h 1f807f4h 1000h
[SD0] BD[5](0x1fd37a0h): 600h 1fd37b0h 1f817f4h 1000h
[SD0] BD[6](0x1fd37b0h): e600h 1fd37c0h 1f827f4h 1000h
[SD0] BD[7](0x1fd37c0h): ca01h 0h 1f837f4h 1000h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3148)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(25): RSP(1) = 0xc00 AUTO(1)
	[CARD_STATUS] 'Rcv' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 32768 bytes (DONE)
[SD0] Write data 64 blks to 0x8018000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(25): ARG(0x8018000), RAW(0x12003099), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): a700h 1fd3760h 1f7c7f4h 1000h
[SD0] BD[1](0x1fd3760h): 8700h 1fd3770h 1f7d7f4h 1000h
[SD0] BD[2](0x1fd3770h): 6700h 1fd3780h 1f7e7f4h 1000h
[SD0] BD[3](0x1fd3780h): 4700h 1fd3790h 1f7f7f4h 1000h
[SD0] BD[4](0x1fd3790h): 2600h 1fd37a0h 1f807f4h 1000h
[SD0] BD[5](0x1fd37a0h): 600h 1fd37b0h 1f817f4h 1000h
[SD0] BD[6](0x1fd37b0h): e600h 1fd37c0h 1f827f4h 1000h
[SD0] BD[7](0x1fd37c0h): ca01h 0h 1f837f4h 1000h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x3148)
[SD0]<CHECKME> Unexpected INT(0x3040)
[SD0] CMD(25): RSP(1) = 0xc00 AUTO(1)
	[CARD_STATUS] 'Rcv' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3040)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 32768 bytes (DONE)
[SD0] <PASS> TC2: test multiple block write
[SD0] Read data 64 blks from 0x8000000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(18): ARG(0x8000000), RAW(0x12001092), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): a700h 1fd3760h 1f7c7f4h 1000h
[SD0] BD[1](0x1fd3760h): 8700h 1fd3770h 1f7d7f4h 1000h
[SD0] BD[2](0x1fd3770h): 6700h 1fd3780h 1f7e7f4h 1000h
[SD0] BD[3](0x1fd3780h): 4700h 1fd3790h 1f7f7f4h 1000h
[SD0] BD[4](0x1fd3790h): 2600h 1fd37a0h 1f807f4h 1000h
[SD0] BD[5](0x1fd37a0h): 600h 1fd37b0h 1f817f4h 1000h
[SD0] BD[6](0x1fd37b0h): e600h 1fd37c0h 1f827f4h 1000h
[SD0] BD[7](0x1fd37c0h): ca01h 0h 1f837f4h 1000h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x31c8)
[SD0]<CHECKME> Unexpected INT(0x30c0)
[SD0] CMD(18): RSP(1) = 0xb00 AUTO(1)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Data' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x30c0)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] DMA Stopped
[SD0] Read data 64 blks from 0x8008000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(18): ARG(0x8008000), RAW(0x12001092), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): a700h 1fd3760h 1f7c7f4h 1000h
[SD0] BD[1](0x1fd3760h): 8700h 1fd3770h 1f7d7f4h 1000h
[SD0] BD[2](0x1fd3770h): 6700h 1fd3780h 1f7e7f4h 1000h
[SD0] BD[3](0x1fd3780h): 4700h 1fd3790h 1f7f7f4h 1000h
[SD0] BD[4](0x1fd3790h): 2600h 1fd37a0h 1f807f4h 1000h
[SD0] BD[5](0x1fd37a0h): 600h 1fd37b0h 1f817f4h 1000h
[SD0] BD[6](0x1fd37b0h): e600h 1fd37c0h 1f827f4h 1000h
[SD0] BD[7](0x1fd37c0h): ca01h 0h 1f837f4h 1000h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x31c8)
[SD0]<CHECKME> Unexpected INT(0x30c0)
[SD0] CMD(18): RSP(1) = 0xb00 AUTO(1)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Data' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x30c0)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] DMA Stopped
[SD0] Read data 64 blks from 0x8010000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(18): ARG(0x8010000), RAW(0x12001092), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): a700h 1fd3760h 1f7c7f4h 1000h
[SD0] BD[1](0x1fd3760h): 8700h 1fd3770h 1f7d7f4h 1000h
[SD0] BD[2](0x1fd3770h): 6700h 1fd3780h 1f7e7f4h 1000h
[SD0] BD[3](0x1fd3780h): 4700h 1fd3790h 1f7f7f4h 1000h
[SD0] BD[4](0x1fd3790h): 2600h 1fd37a0h 1f807f4h 1000h
[SD0] BD[5](0x1fd37a0h): 600h 1fd37b0h 1f817f4h 1000h
[SD0] BD[6](0x1fd37b0h): e600h 1fd37c0h 1f827f4h 1000h
[SD0] BD[7](0x1fd37c0h): ca01h 0h 1f837f4h 1000h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x31c8)
[SD0]<CHECKME> Unexpected INT(0x30c0)
[SD0] CMD(18): RSP(1) = 0xb00 AUTO(1)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Data' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x30c0)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] DMA Stopped
[SD0] Read data 64 blks from 0x8018000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(18): ARG(0x8018000), RAW(0x12001092), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): a700h 1fd3760h 1f7c7f4h 1000h
[SD0] BD[1](0x1fd3760h): 8700h 1fd3770h 1f7d7f4h 1000h
[SD0] BD[2](0x1fd3770h): 6700h 1fd3780h 1f7e7f4h 1000h
[SD0] BD[3](0x1fd3780h): 4700h 1fd3790h 1f7f7f4h 1000h
[SD0] BD[4](0x1fd3790h): 2600h 1fd37a0h 1f807f4h 1000h
[SD0] BD[5](0x1fd37a0h): 600h 1fd37b0h 1f817f4h 1000h
[SD0] BD[6](0x1fd37b0h): e600h 1fd37c0h 1f827f4h 1000h
[SD0] BD[7](0x1fd37c0h): ca01h 0h 1f837f4h 1000h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x31c8)
[SD0]<CHECKME> Unexpected INT(0x30c0)
[SD0] CMD(18): RSP(1) = 0xb00 AUTO(1)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Data' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x30c0)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] DMA Stopped
[SD0] <PASS> TC3: test multiple block read
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x180)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write data 64 blks to 0x8000000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(25): ARG(0x8000000), RAW(0x12003099), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): a700h 1fd3760h 1f7c7f4h 1000h
[SD0] BD[1](0x1fd3760h): 8700h 1fd3770h 1f7d7f4h 1000h
[SD0] BD[2](0x1fd3770h): 6700h 1fd3780h 1f7e7f4h 1000h
[SD0] BD[3](0x1fd3780h): 4700h 1fd3790h 1f7f7f4h 1000h
[SD0] BD[4](0x1fd3790h): 2600h 1fd37a0h 1f807f4h 1000h
[SD0] BD[5](0x1fd37a0h): 600h 1fd37b0h 1f817f4h 1000h
[SD0] BD[6](0x1fd37b0h): e600h 1fd37c0h 1f827f4h 1000h
[SD0] BD[7](0x1fd37c0h): ca01h 0h 1f837f4h 1000h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x1c0)
[SD0]<CHECKME> Unexpected INT(0xc0)
[SD0] CMD(25): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x30c8)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] DMA AUTO CMD Rdy, Resp(c00h)
	[CARD_STATUS] 'Rcv' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x180)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 32768 bytes (DONE)
[SD0] Read data 64 blks from 0x8000000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(18): ARG(0x8000000), RAW(0x12001092), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): a700h 1fd3760h 1f7c7f4h 1000h
[SD0] BD[1](0x1fd3760h): 8700h 1fd3770h 1f7d7f4h 1000h
[SD0] BD[2](0x1fd3770h): 6700h 1fd3780h 1f7e7f4h 1000h
[SD0] BD[3](0x1fd3780h): 4700h 1fd3790h 1f7f7f4h 1000h
[SD0] BD[4](0x1fd3790h): 2600h 1fd37a0h 1f807f4h 1000h
[SD0] BD[5](0x1fd37a0h): 600h 1fd37b0h 1f817f4h 1000h
[SD0] BD[6](0x1fd37b0h): e600h 1fd37c0h 1f827f4h 1000h
[SD0] BD[7](0x1fd37c0h): ca01h 0h 1f837f4h 1000h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x31c8)
[SD0]<CHECKME> Unexpected INT(0x30c0)
[SD0] CMD(18): RSP(1) = 0xb00 AUTO(1)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Data' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x30c0)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] DMA Stopped
[SD0] Write data 64 blks to 0x8008000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(25): ARG(0x8008000), RAW(0x12003099), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): a700h 1fd3760h 1f7c7f4h 1000h
[SD0] BD[1](0x1fd3760h): 8700h 1fd3770h 1f7d7f4h 1000h
[SD0] BD[2](0x1fd3770h): 6700h 1fd3780h 1f7e7f4h 1000h
[SD0] BD[3](0x1fd3780h): 4700h 1fd3790h 1f7f7f4h 1000h
[SD0] BD[4](0x1fd3790h): 2600h 1fd37a0h 1f807f4h 1000h
[SD0] BD[5](0x1fd37a0h): 600h 1fd37b0h 1f817f4h 1000h
[SD0] BD[6](0x1fd37b0h): e600h 1fd37c0h 1f827f4h 1000h
[SD0] BD[7](0x1fd37c0h): ca01h 0h 1f837f4h 1000h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x31c8)
[SD0]<CHECKME> Unexpected INT(0x30c0)
[SD0] CMD(25): RSP(1) = 0xc00 AUTO(1)
	[CARD_STATUS] 'Rcv' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x30c0)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x180)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 32768 bytes (DONE)
[SD0] Read data 64 blks from 0x8008000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(18): ARG(0x8008000), RAW(0x12001092), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): a700h 1fd3760h 1f7c7f4h 1000h
[SD0] BD[1](0x1fd3760h): 8700h 1fd3770h 1f7d7f4h 1000h
[SD0] BD[2](0x1fd3770h): 6700h 1fd3780h 1f7e7f4h 1000h
[SD0] BD[3](0x1fd3780h): 4700h 1fd3790h 1f7f7f4h 1000h
[SD0] BD[4](0x1fd3790h): 2600h 1fd37a0h 1f807f4h 1000h
[SD0] BD[5](0x1fd37a0h): 600h 1fd37b0h 1f817f4h 1000h
[SD0] BD[6](0x1fd37b0h): e600h 1fd37c0h 1f827f4h 1000h
[SD0] BD[7](0x1fd37c0h): ca01h 0h 1f837f4h 1000h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x31c8)
[SD0]<CHECKME> Unexpected INT(0x30c0)
[SD0] CMD(18): RSP(1) = 0xb00 AUTO(1)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Data' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x30c0)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] DMA Stopped
[SD0] Write data 64 blks to 0x8010000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(25): ARG(0x8010000), RAW(0x12003099), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): a700h 1fd3760h 1f7c7f4h 1000h
[SD0] BD[1](0x1fd3760h): 8700h 1fd3770h 1f7d7f4h 1000h
[SD0] BD[2](0x1fd3770h): 6700h 1fd3780h 1f7e7f4h 1000h
[SD0] BD[3](0x1fd3780h): 4700h 1fd3790h 1f7f7f4h 1000h
[SD0] BD[4](0x1fd3790h): 2600h 1fd37a0h 1f807f4h 1000h
[SD0] BD[5](0x1fd37a0h): 600h 1fd37b0h 1f817f4h 1000h
[SD0] BD[6](0x1fd37b0h): e600h 1fd37c0h 1f827f4h 1000h
[SD0] BD[7](0x1fd37c0h): ca01h 0h 1f837f4h 1000h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x180)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] CMD(25): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc5750, Active: 1
[SD0] INT(0xc0)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3088)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] DMA AUTO CMD Rdy, Resp(c00h)
	[CARD_STATUS] 'Rcv' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x180)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 32768 bytes (DONE)
[SD0] Read data 64 blks from 0x8010000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(18): ARG(0x8010000), RAW(0x12001092), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): a700h 1fd3760h 1f7c7f4h 1000h
[SD0] BD[1](0x1fd3760h): 8700h 1fd3770h 1f7d7f4h 1000h
[SD0] BD[2](0x1fd3770h): 6700h 1fd3780h 1f7e7f4h 1000h
[SD0] BD[3](0x1fd3780h): 4700h 1fd3790h 1f7f7f4h 1000h
[SD0] BD[4](0x1fd3790h): 2600h 1fd37a0h 1f807f4h 1000h
[SD0] BD[5](0x1fd37a0h): 600h 1fd37b0h 1f817f4h 1000h
[SD0] BD[6](0x1fd37b0h): e600h 1fd37c0h 1f827f4h 1000h
[SD0] BD[7](0x1fd37c0h): ca01h 0h 1f837f4h 1000h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x31c8)
[SD0]<CHECKME> Unexpected INT(0x30c0)
[SD0] CMD(18): RSP(1) = 0xb00 AUTO(1)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Data' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x30c0)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] DMA Stopped
[SD0] Write data 64 blks to 0x8018000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(25): ARG(0x8018000), RAW(0x12003099), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): a700h 1fd3760h 1f7c7f4h 1000h
[SD0] BD[1](0x1fd3760h): 8700h 1fd3770h 1f7d7f4h 1000h
[SD0] BD[2](0x1fd3770h): 6700h 1fd3780h 1f7e7f4h 1000h
[SD0] BD[3](0x1fd3780h): 4700h 1fd3790h 1f7f7f4h 1000h
[SD0] BD[4](0x1fd3790h): 2600h 1fd37a0h 1f807f4h 1000h
[SD0] BD[5](0x1fd37a0h): 600h 1fd37b0h 1f817f4h 1000h
[SD0] BD[6](0x1fd37b0h): e600h 1fd37c0h 1f827f4h 1000h
[SD0] BD[7](0x1fd37c0h): ca01h 0h 1f837f4h 1000h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x31c8)
[SD0]<CHECKME> Unexpected INT(0x30c0)
[SD0] CMD(25): RSP(1) = 0xc00 AUTO(1)
	[CARD_STATUS] 'Rcv' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x30c0)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x180)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 32768 bytes (DONE)
[SD0] Read data 64 blks from 0x8018000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] CMD(18): ARG(0x8018000), RAW(0x12001092), RSP(1)
[SD0] GD[0](0x1fc5750h): b703h 1fc576ch 1fd3750h 0h 0h 0h 0h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): a700h 1fd3760h 1f7c7f4h 1000h
[SD0] BD[1](0x1fd3760h): 8700h 1fd3770h 1f7d7f4h 1000h
[SD0] BD[2](0x1fd3770h): 6700h 1fd3780h 1f7e7f4h 1000h
[SD0] BD[3](0x1fd3780h): 4700h 1fd3790h 1f7f7f4h 1000h
[SD0] BD[4](0x1fd3790h): 2600h 1fd37a0h 1f807f4h 1000h
[SD0] BD[5](0x1fd37a0h): 600h 1fd37b0h 1f817f4h 1000h
[SD0] BD[6](0x1fd37b0h): e600h 1fd37c0h 1f827f4h 1000h
[SD0] BD[7](0x1fd37c0h): ca01h 0h 1f837f4h 1000h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x31c8)
[SD0]<CHECKME> Unexpected INT(0x30c0)
[SD0] CMD(18): RSP(1) = 0xb00 AUTO(1)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Data' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x30c0)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] DMA Stopped
[SD0] <PASS> TC4: test multiple block interleave write-read
[TST] ----------------------------------------------
[TST] Report -  Auto CMD12 Test 
[TST] ----------------------------------------------
[TST] ----------------------------------------------
[TST] Test Result: TOTAL(1/1), PASS(1), FAIL(0) 
[TST] ----------------------------------------------
[TST] ==============================================
[TST] BEGIN: 1/1, No Stop(0)
[TST] ----------------------------------------------
[TST] Mode    : 4
[TST] Clock   : 48000 kHz
[TST] BusWidth: 4 bits
[TST] BurstSz : 64 bytes
[TST] BlkAddr : 40000h
[TST] BlkSize : 512bytes
[TST] TstBlks : 256
[TST] AutoCMD : 12(1), 23(0)
[TST] ----------------------------------------------
[SD0] Bus Width: 1
[SD0] SET_CLK(260kHz): SCLK(255kHz) MODE(0) DDR(0) DIV(47) DS(0) RS(0)
[SD0] Set read data timeout: 100000000ns 0clks -> 1 x 65536 cycles
[SD0] CMD(0): ARG(0x0), RAW(0x0), RSP(0)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(0): RSP(0)
[SD0] CMD(8): ARG(0x1aa), RAW(0x88), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(8): RSP(1) = 0x1aa AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] Switch error
	[CARD_STATUS] App Command
	[CARD_STATUS] 'Idle' State
[SD0] CMD(5): ARG(0x0), RAW(0x205), RSP(4)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x200)
[SD0] CMD(5): RSP(4) ERR(CMDTO) AUTO(0)
[SD0] CMD(5): ARG(0x0), RAW(0x205), RSP(4)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x200)
[SD0] CMD(5): RSP(4) ERR(CMDTO) AUTO(0)
[SD0] CMD(5): ARG(0x0), RAW(0x205), RSP(4)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x200)
[SD0] CMD(5): RSP(4) ERR(CMDTO) AUTO(0)
[SD0] CMD(5): ARG(0x0), RAW(0x205), RSP(4)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x200)
[SD0] CMD(5): RSP(4) ERR(CMDTO) AUTO(0)
[SD0] CMD(5): ARG(0x0), RAW(0x205), RSP(4)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x200)
[SD0] CMD(5): RSP(4) ERR(CMDTO) AUTO(0)
[SD0] CMD(5): ARG(0x0), RAW(0x205), RSP(4)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x200)
[SD0] CMD(5): RSP(4) ERR(CMDTO) AUTO(0)
[SD0] CMD(55): ARG(0x0), RAW(0xb7), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(55): RSP(1) = 0x120 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] App Command
	[CARD_STATUS] 'Idle' State
[SD0] CMD(41): ARG(0x0), RAW(0x1a9), RSP(3)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(41): RSP(3) = 0xff8000 AUTO(0)
	[OCR] 2.7-2.8 volt
	[OCR] 2.8-2.9 volt
	[OCR] 2.9-3.0 volt
	[OCR] 3.0-3.1 volt
	[OCR] 3.1-3.2 volt
	[OCR] 3.2-3.3 volt
	[OCR] 3.3-3.4 volt
	[OCR] 3.4-3.5 volt
	[OCR] 3.5-3.6 volt
	[OCR] Card Power Up Status (Busy)
[SD0] CMD(0): ARG(0x0), RAW(0x0), RSP(0)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(0): RSP(0)
[SD0] CMD(8): ARG(0x1aa), RAW(0x88), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(8): RSP(1) = 0x1aa AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] Switch error
	[CARD_STATUS] App Command
	[CARD_STATUS] 'Idle' State
[SD0] CMD(55): ARG(0x0), RAW(0xb7), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(55): RSP(1) = 0x120 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] App Command
	[CARD_STATUS] 'Idle' State
[SD0] CMD(41): ARG(0x51200000), RAW(0x1a9), RSP(3)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(41): RSP(3) = 0xff8000 AUTO(0)
	[OCR] 2.7-2.8 volt
	[OCR] 2.8-2.9 volt
	[OCR] 2.9-3.0 volt
	[OCR] 3.0-3.1 volt
	[OCR] 3.1-3.2 volt
	[OCR] 3.2-3.3 volt
	[OCR] 3.3-3.4 volt
	[OCR] 3.4-3.5 volt
	[OCR] 3.5-3.6 volt
	[OCR] Card Power Up Status (Busy)
[SD0] CMD(55): ARG(0x0), RAW(0xb7), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(55): RSP(1) = 0x120 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] App Command
	[CARD_STATUS] 'Idle' State
[SD0] CMD(41): ARG(0x51200000), RAW(0x1a9), RSP(3)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(41): RSP(3) = 0x80ff8000 AUTO(0)
	[OCR] 2.7-2.8 volt
	[OCR] 2.8-2.9 volt
	[OCR] 2.9-3.0 volt
	[OCR] 3.0-3.1 volt
	[OCR] 3.1-3.2 volt
	[OCR] 3.2-3.3 volt
	[OCR] 3.3-3.4 volt
	[OCR] 3.4-3.5 volt
	[OCR] 3.5-3.6 volt
	[OCR] Card Power Up Status (Idle)
[SD0] CMD(2): ARG(0x0), RAW(0x102), RSP(2)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(2): RSP(2) = 0x1b534d30 0x30303030 0x1011d000 0x1200b4c7
[SD0] CMD(3): ARG(0x0), RAW(0x83), RSP(6)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(3): RSP(6) = 0x20520 AUTO(0)
	[RCA] 0x2
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] App Command
	[CARD_STATUS] 'Ident' State
[SD0] CMD(9): ARG(0x20000), RAW(0x109), RSP(2)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(9): RSP(2) = 0x7fff32 0x5b5a83ba 0xf6dbdfff 0xe8000b5
[CSD] CSD v1.0
[CSD] TACC_NS: 80000000 ns, TACC_CLKS: 25500 clks
[CSD] Read Blk Len = 1024, Write Blk Len = 1024
[CSD] CMD Class:'basic' 'block read' 'block write' 'erase' 'lock card' 'app-spec' 'switch' 
[SD0] CMD(7): ARG(0x20000), RAW(0x387), RSP(8)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(7): RSP(8) = 0x700 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Stby' State
[SD0] Set read data timeout: 100000000ns 0clks -> 1 x 65536 cycles
[SD0] CMD(55): ARG(0x20000), RAW(0x800b7), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(55): RSP(1) = 0x920 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] App Command
	[CARD_STATUS] 'Tran' State
[SD0] CMD(51): ARG(0x0), RAW(0x808b3), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x1100)
[SD0]<CHECKME> Unexpected INT(0x1000)
[SD0] CMD(51): RSP(1) = 0x920 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] App Command
	[CARD_STATUS] 'Tran' State
[SD0] Read left bytes, RXFIFOCNT: 0, Left: 0/8
[SD0] SCR: 802502 0 (raw)
[SD0] SCR: 0 2258000 (ntohl)
[SD0] SD_SPEC(2) SD_SPEC3(1) SD_BUS_WIDTH=5
[SD0] SD_SECU(2) EX_SECU(0), CMD_SUPP(0): CMD23(0), CMD20(0)
[SD0] Set read data timeout: 100000000ns 0clks -> 1 x 65536 cycles
[SD0] CMD(6): ARG(0xfffff1), RAW(0x400886), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x1100)
[SD0]<CHECKME> Unexpected INT(0x1000)
[SD0] CMD(6): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Read 64 bytes, RXFIFOCNT: 0,  Left: 0/64
  [511-384] 1806400h 1800180h 1800180h 380h
  [383-256] 1h 0h 0h 0h
  [255-128] 0h 0h 0h 0h
  [127-0] 0h 0h 0h 0h
  [511-448] 0h 64h 80h 1h 80h 1h 80h 1h
  [447-384] 80h 1h 80h 1h 80h 3h 0h 0h
  [383-320] 1h 0h 0h 0h 0h 0h 0h 0h
  [319-256] 0h 0h 0h 0h 0h 0h 0h 0h
  [255-192] 0h 0h 0h 0h 0h 0h 0h 0h
  [191-128] 0h 0h 0h 0h 0h 0h 0h 0h
  [127-64] 0h 0h 0h 0h 0h 0h 0h 0h
  [63-0] 0h 0h 0h 0h 0h 0h 0h 0h
[SD0] Support: Default/SDR12
[SD0] Support: HS/SDR25
[SD0] Support: Type-B Drv
[SD0] Support: 200mA current limit
[SD0] Set read data timeout: 100000000ns 0clks -> 1 x 65536 cycles
[SD0] CMD(6): ARG(0x80fffff1), RAW(0x400886), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x1100)
[SD0]<CHECKME> Unexpected INT(0x1000)
[SD0] CMD(6): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Read 64 bytes, RXFIFOCNT: 0,  Left: 0/64
  [511-384] 1806400h 1800180h 1800180h 380h
  [383-256] 1h 0h 0h 0h
  [255-128] 0h 0h 0h 0h
  [127-0] 0h 0h 0h 0h
  [511-448] 0h 64h 80h 1h 80h 1h 80h 1h
  [447-384] 80h 1h 80h 1h 80h 3h 0h 0h
  [383-320] 1h 0h 0h 0h 0h 0h 0h 0h
  [319-256] 0h 0h 0h 0h 0h 0h 0h 0h
  [255-192] 0h 0h 0h 0h 0h 0h 0h 0h
  [191-128] 0h 0h 0h 0h 0h 0h 0h 0h
  [127-64] 0h 0h 0h 0h 0h 0h 0h 0h
  [63-0] 0h 0h 0h 0h 0h 0h 0h 0h
[SD0] Switch to HS mode!
[SD0] CMD(55): ARG(0x20000), RAW(0x4000b7), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(55): RSP(1) = 0x920 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] App Command
	[CARD_STATUS] 'Tran' State
[SD0] CMD(6): ARG(0x2), RAW(0x400086), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(6): RSP(1) = 0x920 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] App Command
	[CARD_STATUS] 'Tran' State
[SD0] Bus Width: 4
[SD0] CMD(16): ARG(0x200), RAW(0x400090), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(16): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] CMD(55): ARG(0x20000), RAW(0x20000b7), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(55): RSP(1) = 0x920 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] App Command
	[CARD_STATUS] 'Tran' State
[SD0] CMD(42): ARG(0x0), RAW(0x20000aa), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(42): RSP(1) = 0x920 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] App Command
	[CARD_STATUS] 'Tran' State
[SD0] Size: 1910 MB, Max.Speed: 50000 kHz, blklen(512), nblks(3911680), ro(0)
[SD0] Initialized
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] CMD(55): ARG(0x20000), RAW(0x20000b7), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(55): RSP(1) = 0x920 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] App Command
	[CARD_STATUS] 'Tran' State
[SD0] CMD(6): ARG(0x2), RAW(0x2000086), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(6): RSP(1) = 0x920 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] App Command
	[CARD_STATUS] 'Tran' State
[SD0] Bus Width: 4
[SD0] CMD(16): ARG(0x200), RAW(0x2000090), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(16): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] CMD(32): ARG(0x8000000), RAW(0x20000a0), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(32): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] CMD(33): ARG(0x8020000), RAW(0x20000a1), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(33): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] CMD(38): ARG(0x0), RAW(0x20003a6), RSP(8)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(38): RSP(8) = 0x800 AUTO(0)
	[CARD_STATUS] 'Tran' State
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[TST] 0x8000000 - 0x8020000 Erased
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write data 1 blks to 0x8000000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8000000h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8000200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8000200h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8000400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8000400h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8000600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8000600h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8000800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8000800h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8000a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8000a00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8000c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8000c00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8000e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8000e00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8001000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8001000h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8001200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8001200h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8001400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8001400h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8001600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8001600h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8001800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8001800h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8001a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8001a00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8001c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8001c00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8001e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8001e00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8002000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8002000h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8002200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8002200h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8002400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8002400h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8002600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8002600h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8002800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8002800h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8002a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8002a00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8002c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8002c00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8002e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8002e00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8003000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8003000h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8003200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8003200h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8003400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8003400h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8003600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8003600h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8003800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8003800h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8003a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8003a00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8003c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8003c00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8003e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8003e00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8004000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8004000h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8004200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8004200h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8004400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8004400h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8004600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8004600h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8004800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8004800h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8004a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8004a00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8004c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8004c00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8004e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8004e00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8005000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8005000h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8005200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8005200h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8005400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8005400h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8005600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8005600h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8005800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8005800h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8005a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8005a00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8005c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8005c00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8005e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8005e00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8006000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8006000h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8006200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8006200h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8006400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8006400h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8006600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8006600h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8006800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8006800h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8006a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8006a00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8006c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8006c00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8006e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8006e00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8007000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8007000h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8007200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8007200h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8007400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8007400h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8007600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8007600h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8007800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8007800h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8007a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8007a00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8007c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8007c00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8007e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8007e00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8008000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8008000h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8008200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8008200h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8008400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8008400h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8008600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8008600h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8008800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8008800h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8008a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8008a00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8008c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8008c00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8008e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8008e00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8009000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8009000h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8009200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8009200h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8009400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8009400h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8009600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8009600h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8009800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8009800h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8009a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8009a00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8009c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8009c00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8009e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8009e00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800a000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800a000h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800a200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800a200h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800a400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800a400h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800a600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800a600h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800a800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800a800h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800aa00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800aa00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800ac00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800ac00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800ae00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800ae00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800b000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800b000h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800b200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800b200h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800b400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800b400h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800b600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800b600h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800b800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800b800h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800ba00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800ba00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800bc00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800bc00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800be00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800be00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800c000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800c000h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800c200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800c200h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800c400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800c400h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800c600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800c600h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800c800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800c800h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800ca00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800ca00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800cc00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800cc00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800ce00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800ce00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800d000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800d000h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800d200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800d200h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800d400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800d400h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800d600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800d600h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800d800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800d800h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800da00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800da00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800dc00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800dc00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800de00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800de00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800e000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800e000h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800e200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800e200h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800e400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800e400h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800e600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800e600h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800e800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800e800h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800ea00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800ea00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800ec00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800ec00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800ee00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800ee00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800f000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800f000h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800f200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800f200h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800f400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800f400h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800f600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800f600h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800f800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800f800h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800fa00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800fa00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800fc00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800fc00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x800fe00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800fe00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8010000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8010000h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8010200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8010200h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8010400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8010400h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8010600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8010600h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8010800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8010800h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8010a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8010a00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8010c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8010c00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8010e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8010e00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8011000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8011000h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8011200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8011200h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8011400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8011400h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8011600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8011600h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8011800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8011800h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8011a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8011a00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8011c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8011c00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8011e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8011e00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8012000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8012000h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8012200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8012200h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8012400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8012400h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8012600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8012600h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8012800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8012800h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8012a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8012a00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8012c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8012c00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8012e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8012e00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8013000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8013000h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8013200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8013200h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8013400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8013400h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8013600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8013600h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8013800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8013800h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8013a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8013a00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8013c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8013c00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8013e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8013e00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8014000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8014000h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8014200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8014200h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8014400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8014400h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8014600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8014600h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8014800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8014800h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8014a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8014a00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8014c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8014c00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8014e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8014e00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8015000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8015000h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8015200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8015200h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8015400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8015400h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8015600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8015600h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8015800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8015800h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8015a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8015a00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8015c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8015c00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8015e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8015e00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8016000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8016000h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8016200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8016200h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8016400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8016400h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8016600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8016600h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8016800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8016800h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8016a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8016a00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8016c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8016c00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8016e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8016e00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8017000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8017000h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8017200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8017200h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8017400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8017400h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8017600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8017600h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8017800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8017800h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8017a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8017a00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8017c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8017c00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8017e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8017e00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8018000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8018000h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8018200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8018200h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8018400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8018400h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8018600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8018600h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8018800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8018800h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8018a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8018a00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8018c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8018c00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8018e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8018e00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8019000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8019000h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8019200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8019200h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8019400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8019400h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8019600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8019600h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8019800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8019800h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8019a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8019a00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8019c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8019c00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x8019e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8019e00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801a000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801a000h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801a200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801a200h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801a400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801a400h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801a600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801a600h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801a800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801a800h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801aa00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801aa00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801ac00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801ac00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801ae00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801ae00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801b000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801b000h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801b200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801b200h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801b400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801b400h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801b600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801b600h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801b800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801b800h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801ba00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801ba00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801bc00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801bc00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801be00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801be00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801c000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801c000h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801c200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801c200h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801c400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801c400h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801c600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801c600h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801c800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801c800h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801ca00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801ca00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801cc00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801cc00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801ce00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801ce00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801d000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801d000h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801d200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801d200h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801d400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801d400h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801d600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801d600h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801d800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801d800h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801da00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801da00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801dc00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801dc00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801de00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801de00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801e000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801e000h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801e200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801e200h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801e400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801e400h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801e600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801e600h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801e800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801e800h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801ea00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801ea00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801ec00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801ec00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801ee00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801ee00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801f000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801f000h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801f200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801f200h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801f400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801f400h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801f600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801f600h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801f800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801f800h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801fa00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801fa00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801fc00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801fc00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] Write data 1 blks to 0x801fe00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(24), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801fe00h 1h 2002898h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 512 bytes (DONE)
[SD0] <PASS> TC0: test single block write
[SD0] Read data 1 blks from 0x8000000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8000000h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8000200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8000200h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8000400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8000400h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8000600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8000600h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8000800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8000800h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8000a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8000a00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8000c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8000c00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8000e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8000e00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8001000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8001000h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8001200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8001200h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8001400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8001400h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8001600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8001600h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8001800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8001800h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8001a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8001a00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8001c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8001c00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8001e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8001e00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8002000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8002000h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8002200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8002200h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8002400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8002400h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8002600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8002600h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8002800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8002800h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8002a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8002a00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8002c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8002c00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8002e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8002e00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8003000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8003000h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8003200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8003200h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8003400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8003400h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8003600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8003600h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8003800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8003800h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8003a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8003a00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8003c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8003c00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8003e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8003e00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8004000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8004000h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8004200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8004200h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8004400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8004400h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8004600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8004600h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8004800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8004800h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8004a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8004a00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8004c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8004c00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8004e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8004e00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8005000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8005000h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8005200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8005200h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8005400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8005400h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8005600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8005600h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8005800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8005800h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8005a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8005a00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8005c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8005c00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8005e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8005e00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8006000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8006000h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8006200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8006200h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8006400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8006400h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8006600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8006600h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8006800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8006800h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8006a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8006a00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8006c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8006c00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8006e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8006e00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8007000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8007000h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8007200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8007200h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8007400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8007400h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8007600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8007600h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8007800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8007800h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8007a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8007a00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8007c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8007c00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8007e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8007e00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8008000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8008000h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8008200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8008200h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8008400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8008400h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8008600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8008600h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8008800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8008800h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8008a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8008a00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8008c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8008c00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8008e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8008e00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8009000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8009000h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8009200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8009200h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8009400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8009400h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8009600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8009600h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8009800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8009800h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8009a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8009a00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8009c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8009c00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8009e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8009e00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800a000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800a000h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800a200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800a200h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800a400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800a400h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800a600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800a600h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800a800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800a800h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800aa00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800aa00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800ac00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800ac00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800ae00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800ae00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800b000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800b000h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800b200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800b200h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800b400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800b400h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800b600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800b600h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800b800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800b800h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800ba00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800ba00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800bc00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800bc00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800be00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800be00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800c000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800c000h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800c200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800c200h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800c400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800c400h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800c600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800c600h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800c800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800c800h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800ca00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800ca00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800cc00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800cc00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800ce00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800ce00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800d000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800d000h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800d200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800d200h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800d400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800d400h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800d600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800d600h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800d800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800d800h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800da00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800da00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800dc00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800dc00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800de00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800de00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800e000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800e000h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800e200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800e200h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800e400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800e400h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800e600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800e600h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800e800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800e800h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800ea00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800ea00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800ec00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800ec00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800ee00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800ee00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800f000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800f000h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800f200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800f200h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800f400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800f400h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800f600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800f600h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800f800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800f800h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800fa00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800fa00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800fc00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800fc00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x800fe00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 800fe00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8010000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8010000h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8010200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8010200h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8010400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8010400h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8010600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8010600h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8010800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8010800h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8010a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8010a00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8010c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8010c00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8010e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8010e00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8011000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8011000h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8011200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8011200h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8011400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8011400h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8011600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8011600h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8011800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8011800h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8011a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8011a00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8011c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8011c00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8011e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8011e00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8012000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8012000h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8012200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8012200h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8012400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8012400h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8012600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8012600h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8012800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8012800h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8012a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8012a00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8012c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8012c00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8012e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8012e00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8013000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8013000h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8013200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8013200h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8013400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8013400h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8013600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8013600h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8013800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8013800h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8013a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8013a00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8013c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8013c00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8013e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8013e00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8014000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8014000h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8014200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8014200h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8014400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8014400h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8014600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8014600h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8014800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8014800h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8014a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8014a00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8014c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8014c00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8014e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8014e00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8015000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8015000h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8015200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8015200h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8015400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8015400h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8015600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8015600h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8015800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8015800h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8015a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8015a00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8015c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8015c00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8015e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8015e00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8016000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8016000h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8016200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8016200h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8016400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8016400h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8016600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8016600h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8016800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8016800h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8016a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8016a00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8016c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8016c00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8016e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8016e00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8017000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8017000h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8017200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8017200h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8017400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8017400h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8017600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8017600h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8017800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8017800h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8017a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8017a00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8017c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8017c00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8017e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8017e00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8018000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8018000h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8018200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8018200h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8018400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8018400h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8018600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8018600h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8018800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8018800h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8018a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8018a00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8018c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8018c00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8018e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8018e00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8019000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8019000h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8019200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8019200h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8019400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8019400h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8019600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8019600h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8019800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8019800h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8019a00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8019a00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8019c00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8019c00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x8019e00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 8019e00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801a000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801a000h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801a200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801a200h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801a400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801a400h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801a600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801a600h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801a800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801a800h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801aa00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801aa00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801ac00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801ac00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801ae00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801ae00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801b000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801b000h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801b200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801b200h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801b400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801b400h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801b600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801b600h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801b800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801b800h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801ba00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801ba00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801bc00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801bc00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801be00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801be00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801c000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801c000h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801c200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801c200h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801c400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801c400h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801c600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801c600h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801c800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801c800h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801ca00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801ca00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801cc00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801cc00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801ce00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801ce00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801d000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801d000h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801d200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801d200h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801d400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801d400h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801d600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801d600h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801d800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801d800h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801da00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801da00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801dc00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801dc00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801de00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801de00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801e000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801e000h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801e200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801e200h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801e400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801e400h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801e600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801e600h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801e800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801e800h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801ea00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801ea00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801ec00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801ec00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801ee00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801ee00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801f000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801f000h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801f200
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801f200h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801f400
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801f400h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801f600
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801f600h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801f800
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801f800h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801fa00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801fa00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801fc00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801fc00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] Read data 1 blks from 0x801fe00
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(17), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): ab03h 1fc576ch 1fd3750h c0000h 801fe00h 1h 2000891h
[SD0] GD[1](0x1fc576ch): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): 4901h 0h 1f7c7f4h 200h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 0
[SD0] INT(0x3140)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Stopped
[SD0] <PASS> TC1: test single block read
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write data 64 blks to 0x8000000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(25), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): 1aa03h 1fc576ch 1fd3750h c0000h 8000000h 10h 12003099h
[SD0] GD[1](0x1fc576ch): 16e03h 1fc5788h 1fd3770h c0000h 8002000h 10h 12003099h
[SD0] GD[2](0x1fc5788h): 13203h 1fc57a4h 1fd3790h c0000h 8004000h 10h 12003099h
[SD0] GD[3](0x1fc57a4h): f703h 1fc57c0h 1fd37b0h c0000h 8006000h 10h 12003099h
[SD0] GD[4](0x1fc57c0h): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): a700h 1fd3760h 1f7c7f4h 1000h
[SD0] BD[1](0x1fd3760h): 2b01h 0h 1f7d7f4h 1000h
[SD0] BD[2](0x1fd3770h): 6700h 1fd3780h 1f7e7f4h 1000h
[SD0] BD[3](0x1fd3780h): b01h 0h 1f7f7f4h 1000h
[SD0] BD[4](0x1fd3790h): 2600h 1fd37a0h 1f807f4h 1000h
[SD0] BD[5](0x1fd37a0h): ea01h 0h 1f817f4h 1000h
[SD0] BD[6](0x1fd37b0h): e600h 1fd37c0h 1f827f4h 1000h
[SD0] BD[7](0x1fd37c0h): ca01h 0h 1f837f4h 1000h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc576c
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x100)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x1008)
[SD0] DMA AUTO CMD Rdy, Resp(c00h)
	[CARD_STATUS] 'Rcv' State
[SD0] DMA Curr Addr: 0x1fc5788, Active: 1
[SD0] INT(0x100)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc5788, Active: 1
[SD0] INT(0x1008)
[SD0] DMA AUTO CMD Rdy, Resp(c00h)
	[CARD_STATUS] 'Rcv' State
[SD0] DMA Curr Addr: 0x1fc57a4, Active: 1
[SD0] INT(0x100)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc57a4, Active: 1
[SD0] INT(0x3008)
[SD0] DMA AUTO CMD Rdy, Resp(c00h)
	[CARD_STATUS] 'Rcv' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x1148)
[SD0]<CHECKME> Unexpected INT(0x1040)
[SD0] CMD(13): RSP(1) = 0xc00 AUTO(1)
	[CARD_STATUS] 'Rcv' State
	[CARD_STATUS] 'Rcv' State
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x1140)
[SD0]<CHECKME> Unexpected INT(0x1040)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 32768 bytes (DONE)
[SD0] Write data 64 blks to 0x8008000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(25), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): 1aa03h 1fc576ch 1fd3750h c0000h 8008000h 10h 12003099h
[SD0] GD[1](0x1fc576ch): 16e03h 1fc5788h 1fd3770h c0000h 800a000h 10h 12003099h
[SD0] GD[2](0x1fc5788h): 13203h 1fc57a4h 1fd3790h c0000h 800c000h 10h 12003099h
[SD0] GD[3](0x1fc57a4h): f703h 1fc57c0h 1fd37b0h c0000h 800e000h 10h 12003099h
[SD0] GD[4](0x1fc57c0h): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): a700h 1fd3760h 1f7c7f4h 1000h
[SD0] BD[1](0x1fd3760h): 2b01h 0h 1f7d7f4h 1000h
[SD0] BD[2](0x1fd3770h): 6700h 1fd3780h 1f7e7f4h 1000h
[SD0] BD[3](0x1fd3780h): b01h 0h 1f7f7f4h 1000h
[SD0] BD[4](0x1fd3790h): 2600h 1fd37a0h 1f807f4h 1000h
[SD0] BD[5](0x1fd37a0h): ea01h 0h 1f817f4h 1000h
[SD0] BD[6](0x1fd37b0h): e600h 1fd37c0h 1f827f4h 1000h
[SD0] BD[7](0x1fd37c0h): ca01h 0h 1f837f4h 1000h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc57c0
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3148)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA AUTO CMD Rdy, Resp(c00h)
	[CARD_STATUS] 'Rcv' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 32768 bytes (DONE)
[SD0] Write data 64 blks to 0x8010000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(25), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): 1aa03h 1fc576ch 1fd3750h c0000h 8010000h 10h 12003099h
[SD0] GD[1](0x1fc576ch): 16e03h 1fc5788h 1fd3770h c0000h 8012000h 10h 12003099h
[SD0] GD[2](0x1fc5788h): 13203h 1fc57a4h 1fd3790h c0000h 8014000h 10h 12003099h
[SD0] GD[3](0x1fc57a4h): f703h 1fc57c0h 1fd37b0h c0000h 8016000h 10h 12003099h
[SD0] GD[4](0x1fc57c0h): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): a700h 1fd3760h 1f7c7f4h 1000h
[SD0] BD[1](0x1fd3760h): 2b01h 0h 1f7d7f4h 1000h
[SD0] BD[2](0x1fd3770h): 6700h 1fd3780h 1f7e7f4h 1000h
[SD0] BD[3](0x1fd3780h): b01h 0h 1f7f7f4h 1000h
[SD0] BD[4](0x1fd3790h): 2600h 1fd37a0h 1f807f4h 1000h
[SD0] BD[5](0x1fd37a0h): ea01h 0h 1f817f4h 1000h
[SD0] BD[6](0x1fd37b0h): e600h 1fd37c0h 1f827f4h 1000h
[SD0] BD[7](0x1fd37c0h): ca01h 0h 1f837f4h 1000h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc57c0
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x1108)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA AUTO CMD Rdy, Resp(c00h)
	[CARD_STATUS] 'Rcv' State
[SD0] DMA Curr Addr: 0x1fc57c0, Active: 0
[SD0] INT(0x3048)
[SD0] DMA AUTO CMD Rdy, Resp(c00h)
	[CARD_STATUS] 'Rcv' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 32768 bytes (DONE)
[SD0] Write data 64 blks to 0x8018000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(25), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): 1aa03h 1fc576ch 1fd3750h c0000h 8018000h 10h 12003099h
[SD0] GD[1](0x1fc576ch): 16e03h 1fc5788h 1fd3770h c0000h 801a000h 10h 12003099h
[SD0] GD[2](0x1fc5788h): 13203h 1fc57a4h 1fd3790h c0000h 801c000h 10h 12003099h
[SD0] GD[3](0x1fc57a4h): f703h 1fc57c0h 1fd37b0h c0000h 801e000h 10h 12003099h
[SD0] GD[4](0x1fc57c0h): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): a700h 1fd3760h 1f7c7f4h 1000h
[SD0] BD[1](0x1fd3760h): 2b01h 0h 1f7d7f4h 1000h
[SD0] BD[2](0x1fd3770h): 6700h 1fd3780h 1f7e7f4h 1000h
[SD0] BD[3](0x1fd3780h): b01h 0h 1f7f7f4h 1000h
[SD0] BD[4](0x1fd3790h): 2600h 1fd37a0h 1f807f4h 1000h
[SD0] BD[5](0x1fd37a0h): ea01h 0h 1f817f4h 1000h
[SD0] BD[6](0x1fd37b0h): e600h 1fd37c0h 1f827f4h 1000h
[SD0] BD[7](0x1fd37c0h): ca01h 0h 1f837f4h 1000h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc57c0
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x1108)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA AUTO CMD Rdy, Resp(c00h)
	[CARD_STATUS] 'Rcv' State
[SD0] DMA Curr Addr: 0x1fc57c0, Active: 0
[SD0] INT(0x3048)
[SD0] DMA AUTO CMD Rdy, Resp(c00h)
	[CARD_STATUS] 'Rcv' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x100)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 32768 bytes (DONE)
[SD0] <PASS> TC2: test multiple block write
[SD0] Read data 64 blks from 0x8000000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(18), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): 1aa03h 1fc576ch 1fd3750h c0000h 8000000h 10h 12001092h
[SD0] GD[1](0x1fc576ch): 16e03h 1fc5788h 1fd3770h c0000h 8002000h 10h 12001092h
[SD0] GD[2](0x1fc5788h): 13203h 1fc57a4h 1fd3790h c0000h 8004000h 10h 12001092h
[SD0] GD[3](0x1fc57a4h): f703h 1fc57c0h 1fd37b0h c0000h 8006000h 10h 12001092h
[SD0] GD[4](0x1fc57c0h): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): a700h 1fd3760h 1f7c7f4h 1000h
[SD0] BD[1](0x1fd3760h): 2b01h 0h 1f7d7f4h 1000h
[SD0] BD[2](0x1fd3770h): 6700h 1fd3780h 1f7e7f4h 1000h
[SD0] BD[3](0x1fd3780h): b01h 0h 1f7f7f4h 1000h
[SD0] BD[4](0x1fd3790h): 2600h 1fd37a0h 1f807f4h 1000h
[SD0] BD[5](0x1fd37a0h): ea01h 0h 1f817f4h 1000h
[SD0] BD[6](0x1fd37b0h): e600h 1fd37c0h 1f827f4h 1000h
[SD0] BD[7](0x1fd37c0h): ca01h 0h 1f837f4h 1000h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc57c0
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x31c8)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA AUTO CMD Rdy, Resp(b00h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Data' State
[SD0] DMA Stopped
[SD0] Read data 64 blks from 0x8008000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(18), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): 1aa03h 1fc576ch 1fd3750h c0000h 8008000h 10h 12001092h
[SD0] GD[1](0x1fc576ch): 16e03h 1fc5788h 1fd3770h c0000h 800a000h 10h 12001092h
[SD0] GD[2](0x1fc5788h): 13203h 1fc57a4h 1fd3790h c0000h 800c000h 10h 12001092h
[SD0] GD[3](0x1fc57a4h): f703h 1fc57c0h 1fd37b0h c0000h 800e000h 10h 12001092h
[SD0] GD[4](0x1fc57c0h): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): a700h 1fd3760h 1f7c7f4h 1000h
[SD0] BD[1](0x1fd3760h): 2b01h 0h 1f7d7f4h 1000h
[SD0] BD[2](0x1fd3770h): 6700h 1fd3780h 1f7e7f4h 1000h
[SD0] BD[3](0x1fd3780h): b01h 0h 1f7f7f4h 1000h
[SD0] BD[4](0x1fd3790h): 2600h 1fd37a0h 1f807f4h 1000h
[SD0] BD[5](0x1fd37a0h): ea01h 0h 1f817f4h 1000h
[SD0] BD[6](0x1fd37b0h): e600h 1fd37c0h 1f827f4h 1000h
[SD0] BD[7](0x1fd37c0h): ca01h 0h 1f837f4h 1000h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc57c0
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc5750, Active: 1
[SD0] INT(0x1188)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA AUTO CMD Rdy, Resp(b00h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Data' State
[SD0] DMA Curr Addr: 0x1fc57c0, Active: 0
[SD0] INT(0x20c0)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] DMA Stopped
[SD0] Read data 64 blks from 0x8010000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(18), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): 1aa03h 1fc576ch 1fd3750h c0000h 8010000h 10h 12001092h
[SD0] GD[1](0x1fc576ch): 16e03h 1fc5788h 1fd3770h c0000h 8012000h 10h 12001092h
[SD0] GD[2](0x1fc5788h): 13203h 1fc57a4h 1fd3790h c0000h 8014000h 10h 12001092h
[SD0] GD[3](0x1fc57a4h): f703h 1fc57c0h 1fd37b0h c0000h 8016000h 10h 12001092h
[SD0] GD[4](0x1fc57c0h): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): a700h 1fd3760h 1f7c7f4h 1000h
[SD0] BD[1](0x1fd3760h): 2b01h 0h 1f7d7f4h 1000h
[SD0] BD[2](0x1fd3770h): 6700h 1fd3780h 1f7e7f4h 1000h
[SD0] BD[3](0x1fd3780h): b01h 0h 1f7f7f4h 1000h
[SD0] BD[4](0x1fd3790h): 2600h 1fd37a0h 1f807f4h 1000h
[SD0] BD[5](0x1fd37a0h): ea01h 0h 1f817f4h 1000h
[SD0] BD[6](0x1fd37b0h): e600h 1fd37c0h 1f827f4h 1000h
[SD0] BD[7](0x1fd37c0h): ca01h 0h 1f837f4h 1000h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc57c0
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc5750, Active: 1
[SD0] INT(0x1188)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA AUTO CMD Rdy, Resp(b00h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Data' State
[SD0] DMA Curr Addr: 0x1fc57c0, Active: 0
[SD0] INT(0x20c0)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] DMA Stopped
[SD0] Read data 64 blks from 0x8018000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(18), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): 1aa03h 1fc576ch 1fd3750h c0000h 8018000h 10h 12001092h
[SD0] GD[1](0x1fc576ch): 16e03h 1fc5788h 1fd3770h c0000h 801a000h 10h 12001092h
[SD0] GD[2](0x1fc5788h): 13203h 1fc57a4h 1fd3790h c0000h 801c000h 10h 12001092h
[SD0] GD[3](0x1fc57a4h): f703h 1fc57c0h 1fd37b0h c0000h 801e000h 10h 12001092h
[SD0] GD[4](0x1fc57c0h): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): a700h 1fd3760h 1f7c7f4h 1000h
[SD0] BD[1](0x1fd3760h): 2b01h 0h 1f7d7f4h 1000h
[SD0] BD[2](0x1fd3770h): 6700h 1fd3780h 1f7e7f4h 1000h
[SD0] BD[3](0x1fd3780h): b01h 0h 1f7f7f4h 1000h
[SD0] BD[4](0x1fd3790h): 2600h 1fd37a0h 1f807f4h 1000h
[SD0] BD[5](0x1fd37a0h): ea01h 0h 1f817f4h 1000h
[SD0] BD[6](0x1fd37b0h): e600h 1fd37c0h 1f827f4h 1000h
[SD0] BD[7](0x1fd37c0h): ca01h 0h 1f837f4h 1000h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc57c0
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc5750, Active: 1
[SD0] INT(0x1188)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA AUTO CMD Rdy, Resp(b00h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Data' State
[SD0] DMA Curr Addr: 0x1fc57c0, Active: 0
[SD0] INT(0x20c0)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] DMA Stopped
[SD0] <PASS> TC3: test multiple block read
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x180)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write data 64 blks to 0x8000000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(25), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): 1aa03h 1fc576ch 1fd3750h c0000h 8000000h 10h 12003099h
[SD0] GD[1](0x1fc576ch): 16e03h 1fc5788h 1fd3770h c0000h 8002000h 10h 12003099h
[SD0] GD[2](0x1fc5788h): 13203h 1fc57a4h 1fd3790h c0000h 8004000h 10h 12003099h
[SD0] GD[3](0x1fc57a4h): f703h 1fc57c0h 1fd37b0h c0000h 8006000h 10h 12003099h
[SD0] GD[4](0x1fc57c0h): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): a700h 1fd3760h 1f7c7f4h 1000h
[SD0] BD[1](0x1fd3760h): 2b01h 0h 1f7d7f4h 1000h
[SD0] BD[2](0x1fd3770h): 6700h 1fd3780h 1f7e7f4h 1000h
[SD0] BD[3](0x1fd3780h): b01h 0h 1f7f7f4h 1000h
[SD0] BD[4](0x1fd3790h): 2600h 1fd37a0h 1f807f4h 1000h
[SD0] BD[5](0x1fd37a0h): ea01h 0h 1f817f4h 1000h
[SD0] BD[6](0x1fd37b0h): e600h 1fd37c0h 1f827f4h 1000h
[SD0] BD[7](0x1fd37c0h): ca01h 0h 1f837f4h 1000h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc57c0
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x180)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x1088)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] DMA AUTO CMD Rdy, Resp(c00h)
	[CARD_STATUS] 'Rcv' State
[SD0] DMA Curr Addr: 0x1fc5788, Active: 1
[SD0] INT(0x180)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc5788, Active: 1
[SD0] INT(0x1088)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] DMA AUTO CMD Rdy, Resp(c00h)
	[CARD_STATUS] 'Rcv' State
[SD0] DMA Curr Addr: 0x1fc57a4, Active: 1
[SD0] INT(0x180)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA Curr Addr: 0x1fc57a4, Active: 1
[SD0] INT(0x3088)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] DMA AUTO CMD Rdy, Resp(c00h)
	[CARD_STATUS] 'Rcv' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x11c8)
[SD0]<CHECKME> Unexpected INT(0x10c0)
[SD0] CMD(13): RSP(1) = 0xc00 AUTO(1)
	[CARD_STATUS] 'Rcv' State
	[CARD_STATUS] 'Rcv' State
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x11c0)
[SD0]<CHECKME> Unexpected INT(0x10c0)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 32768 bytes (DONE)
[SD0] Read data 64 blks from 0x8000000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(18), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): 1aa03h 1fc576ch 1fd3750h c0000h 8000000h 10h 12001092h
[SD0] GD[1](0x1fc576ch): 16e03h 1fc5788h 1fd3770h c0000h 8002000h 10h 12001092h
[SD0] GD[2](0x1fc5788h): 13203h 1fc57a4h 1fd3790h c0000h 8004000h 10h 12001092h
[SD0] GD[3](0x1fc57a4h): f703h 1fc57c0h 1fd37b0h c0000h 8006000h 10h 12001092h
[SD0] GD[4](0x1fc57c0h): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): a700h 1fd3760h 1f7c7f4h 1000h
[SD0] BD[1](0x1fd3760h): 2b01h 0h 1f7d7f4h 1000h
[SD0] BD[2](0x1fd3770h): 6700h 1fd3780h 1f7e7f4h 1000h
[SD0] BD[3](0x1fd3780h): b01h 0h 1f7f7f4h 1000h
[SD0] BD[4](0x1fd3790h): 2600h 1fd37a0h 1f807f4h 1000h
[SD0] BD[5](0x1fd37a0h): ea01h 0h 1f817f4h 1000h
[SD0] BD[6](0x1fd37b0h): e600h 1fd37c0h 1f827f4h 1000h
[SD0] BD[7](0x1fd37c0h): ca01h 0h 1f837f4h 1000h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc57c0
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x31c8)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA AUTO CMD Rdy, Resp(b00h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Data' State
[SD0] DMA Stopped
[SD0] Write data 64 blks to 0x8008000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(25), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): 1aa03h 1fc576ch 1fd3750h c0000h 8008000h 10h 12003099h
[SD0] GD[1](0x1fc576ch): 16e03h 1fc5788h 1fd3770h c0000h 800a000h 10h 12003099h
[SD0] GD[2](0x1fc5788h): 13203h 1fc57a4h 1fd3790h c0000h 800c000h 10h 12003099h
[SD0] GD[3](0x1fc57a4h): f703h 1fc57c0h 1fd37b0h c0000h 800e000h 10h 12003099h
[SD0] GD[4](0x1fc57c0h): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): a700h 1fd3760h 1f7c7f4h 1000h
[SD0] BD[1](0x1fd3760h): 2b01h 0h 1f7d7f4h 1000h
[SD0] BD[2](0x1fd3770h): 6700h 1fd3780h 1f7e7f4h 1000h
[SD0] BD[3](0x1fd3780h): b01h 0h 1f7f7f4h 1000h
[SD0] BD[4](0x1fd3790h): 2600h 1fd37a0h 1f807f4h 1000h
[SD0] BD[5](0x1fd37a0h): ea01h 0h 1f817f4h 1000h
[SD0] BD[6](0x1fd37b0h): e600h 1fd37c0h 1f827f4h 1000h
[SD0] BD[7](0x1fd37c0h): ca01h 0h 1f837f4h 1000h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc57c0
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x3188)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA AUTO CMD Rdy, Resp(c00h)
	[CARD_STATUS] 'Rcv' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x1c0)
[SD0]<CHECKME> Unexpected INT(0xc0)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 32768 bytes (DONE)
[SD0] Read data 64 blks from 0x8008000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(18), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): 1aa03h 1fc576ch 1fd3750h c0000h 8008000h 10h 12001092h
[SD0] GD[1](0x1fc576ch): 16e03h 1fc5788h 1fd3770h c0000h 800a000h 10h 12001092h
[SD0] GD[2](0x1fc5788h): 13203h 1fc57a4h 1fd3790h c0000h 800c000h 10h 12001092h
[SD0] GD[3](0x1fc57a4h): f703h 1fc57c0h 1fd37b0h c0000h 800e000h 10h 12001092h
[SD0] GD[4](0x1fc57c0h): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): a700h 1fd3760h 1f7c7f4h 1000h
[SD0] BD[1](0x1fd3760h): 2b01h 0h 1f7d7f4h 1000h
[SD0] BD[2](0x1fd3770h): 6700h 1fd3780h 1f7e7f4h 1000h
[SD0] BD[3](0x1fd3780h): b01h 0h 1f7f7f4h 1000h
[SD0] BD[4](0x1fd3790h): 2600h 1fd37a0h 1f807f4h 1000h
[SD0] BD[5](0x1fd37a0h): ea01h 0h 1f817f4h 1000h
[SD0] BD[6](0x1fd37b0h): e600h 1fd37c0h 1f827f4h 1000h
[SD0] BD[7](0x1fd37c0h): ca01h 0h 1f837f4h 1000h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc57c0
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc5750, Active: 1
[SD0] INT(0x11c8)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA AUTO CMD Rdy, Resp(b00h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Data' State
[SD0] DMA Curr Addr: 0x1fc57c0, Active: 0
[SD0] INT(0x2080)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] DMA Stopped
[SD0] Write data 64 blks to 0x8010000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(25), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): 1aa03h 1fc576ch 1fd3750h c0000h 8010000h 10h 12003099h
[SD0] GD[1](0x1fc576ch): 16e03h 1fc5788h 1fd3770h c0000h 8012000h 10h 12003099h
[SD0] GD[2](0x1fc5788h): 13203h 1fc57a4h 1fd3790h c0000h 8014000h 10h 12003099h
[SD0] GD[3](0x1fc57a4h): f703h 1fc57c0h 1fd37b0h c0000h 8016000h 10h 12003099h
[SD0] GD[4](0x1fc57c0h): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): a700h 1fd3760h 1f7c7f4h 1000h
[SD0] BD[1](0x1fd3760h): 2b01h 0h 1f7d7f4h 1000h
[SD0] BD[2](0x1fd3770h): 6700h 1fd3780h 1f7e7f4h 1000h
[SD0] BD[3](0x1fd3780h): b01h 0h 1f7f7f4h 1000h
[SD0] BD[4](0x1fd3790h): 2600h 1fd37a0h 1f807f4h 1000h
[SD0] BD[5](0x1fd37a0h): ea01h 0h 1f817f4h 1000h
[SD0] BD[6](0x1fd37b0h): e600h 1fd37c0h 1f827f4h 1000h
[SD0] BD[7](0x1fd37c0h): ca01h 0h 1f837f4h 1000h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc57c0
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x1188)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA AUTO CMD Rdy, Resp(c00h)
	[CARD_STATUS] 'Rcv' State
[SD0] DMA Curr Addr: 0x1fc57c0, Active: 0
[SD0] INT(0x30c8)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] DMA AUTO CMD Rdy, Resp(c00h)
	[CARD_STATUS] 'Rcv' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x180)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 32768 bytes (DONE)
[SD0] Read data 64 blks from 0x8010000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(18), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): 1aa03h 1fc576ch 1fd3750h c0000h 8010000h 10h 12001092h
[SD0] GD[1](0x1fc576ch): 16e03h 1fc5788h 1fd3770h c0000h 8012000h 10h 12001092h
[SD0] GD[2](0x1fc5788h): 13203h 1fc57a4h 1fd3790h c0000h 8014000h 10h 12001092h
[SD0] GD[3](0x1fc57a4h): f703h 1fc57c0h 1fd37b0h c0000h 8016000h 10h 12001092h
[SD0] GD[4](0x1fc57c0h): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): a700h 1fd3760h 1f7c7f4h 1000h
[SD0] BD[1](0x1fd3760h): 2b01h 0h 1f7d7f4h 1000h
[SD0] BD[2](0x1fd3770h): 6700h 1fd3780h 1f7e7f4h 1000h
[SD0] BD[3](0x1fd3780h): b01h 0h 1f7f7f4h 1000h
[SD0] BD[4](0x1fd3790h): 2600h 1fd37a0h 1f807f4h 1000h
[SD0] BD[5](0x1fd37a0h): ea01h 0h 1f817f4h 1000h
[SD0] BD[6](0x1fd37b0h): e600h 1fd37c0h 1f827f4h 1000h
[SD0] BD[7](0x1fd37c0h): ca01h 0h 1f837f4h 1000h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc57c0
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc5750, Active: 1
[SD0] INT(0x1188)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA AUTO CMD Rdy, Resp(b00h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Data' State
[SD0] DMA Curr Addr: 0x1fc57c0, Active: 0
[SD0] INT(0x20c0)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] DMA Stopped
[SD0] Write data 64 blks to 0x8018000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(25), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): 1aa03h 1fc576ch 1fd3750h c0000h 8018000h 10h 12003099h
[SD0] GD[1](0x1fc576ch): 16e03h 1fc5788h 1fd3770h c0000h 801a000h 10h 12003099h
[SD0] GD[2](0x1fc5788h): 13203h 1fc57a4h 1fd3790h c0000h 801c000h 10h 12003099h
[SD0] GD[3](0x1fc57a4h): f703h 1fc57c0h 1fd37b0h c0000h 801e000h 10h 12003099h
[SD0] GD[4](0x1fc57c0h): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): a700h 1fd3760h 1f7c7f4h 1000h
[SD0] BD[1](0x1fd3760h): 2b01h 0h 1f7d7f4h 1000h
[SD0] BD[2](0x1fd3770h): 6700h 1fd3780h 1f7e7f4h 1000h
[SD0] BD[3](0x1fd3780h): b01h 0h 1f7f7f4h 1000h
[SD0] BD[4](0x1fd3790h): 2600h 1fd37a0h 1f807f4h 1000h
[SD0] BD[5](0x1fd37a0h): ea01h 0h 1f817f4h 1000h
[SD0] BD[6](0x1fd37b0h): e600h 1fd37c0h 1f827f4h 1000h
[SD0] BD[7](0x1fd37c0h): ca01h 0h 1f837f4h 1000h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc57c0
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc576c, Active: 1
[SD0] INT(0x1188)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA AUTO CMD Rdy, Resp(c00h)
	[CARD_STATUS] 'Rcv' State
[SD0] DMA Curr Addr: 0x1fc57c0, Active: 0
[SD0] INT(0x30c8)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] DMA AUTO CMD Rdy, Resp(c00h)
	[CARD_STATUS] 'Rcv' State
[SD0] DMA Stopped
[SD0] CMD(13): ARG(0x20000), RAW(0x200008d), RSP(1)
[WARN] (MSDC_READ32(MSDC_INTEN) & intrs) != intrs LINE:1035 FILE:msdc/msdc.c
[SD0] INT(0x180)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] CMD(13): RSP(1) = 0x900 AUTO(0)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] Write 32768 bytes (DONE)
[SD0] Read data 64 blks from 0x8018000
[SD0] Set read data timeout: 100000000ns 0clks -> 76 x 65536 cycles
[SD0] DMA CMD(18), AUTOCMD12(1), AUTOCMD23(0)
[SD0] GD[0](0x1fc5750h): 1aa03h 1fc576ch 1fd3750h c0000h 8018000h 10h 12001092h
[SD0] GD[1](0x1fc576ch): 16e03h 1fc5788h 1fd3770h c0000h 801a000h 10h 12001092h
[SD0] GD[2](0x1fc5788h): 13203h 1fc57a4h 1fd3790h c0000h 801c000h 10h 12001092h
[SD0] GD[3](0x1fc57a4h): f703h 1fc57c0h 1fd37b0h c0000h 801e000h 10h 12001092h
[SD0] GD[4](0x1fc57c0h): ff00h 0h 0h 0h 0h 0h 0h
[SD0] BD[0](0x1fd3750h): a700h 1fd3760h 1f7c7f4h 1000h
[SD0] BD[1](0x1fd3760h): 2b01h 0h 1f7d7f4h 1000h
[SD0] BD[2](0x1fd3770h): 6700h 1fd3780h 1f7e7f4h 1000h
[SD0] BD[3](0x1fd3780h): b01h 0h 1f7f7f4h 1000h
[SD0] BD[4](0x1fd3790h): 2600h 1fd37a0h 1f807f4h 1000h
[SD0] BD[5](0x1fd37a0h): ea01h 0h 1f817f4h 1000h
[SD0] BD[6](0x1fd37b0h): e600h 1fd37c0h 1f827f4h 1000h
[SD0] BD[7](0x1fd37c0h): ca01h 0h 1f837f4h 1000h
[SD0] DMA_SA   = 0x1fc5750
[SD0] DMA_CA   = 0x1fc57c0
[SD0] DMA_CTRL = 0x80006500
[SD0] DMA_CFG  = 0x0
[SD0] DMA start
[SD0] DMA Curr Addr: 0x1fc5750, Active: 1
[SD0] INT(0x1188)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] DMA ENH CMD Rdy, Resp(900h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Tran' State
[SD0] DMA AUTO CMD Rdy, Resp(b00h)
	[CARD_STATUS] Ready for Data
	[CARD_STATUS] 'Data' State
[SD0] DMA Curr Addr: 0x1fc57c0, Active: 0
[SD0] INT(0x20c0)
[SD0]<CHECKME> Unexpected INT(0x80)
[SD0] DMA Stopped
[SD0] <PASS> TC4: test multiple block interleave write-read
[TST] ----------------------------------------------
[TST] Report -  Auto CMD12 Test 
[TST] ----------------------------------------------
[TST] ----------------------------------------------
[TST] Test Result: TOTAL(1/1), PASS(1), FAIL(0) 
[TST] ----------------------------------------------
Auto Command 12 Test pass!
RT6352 # 