

U-Boot 1.1.3 (Nov 24 2011 - 16:21:09)

Board: Ralink APSoC DRAM:  32 MB
relocate_code Pointer at: 81f38000
spi_wait_nsec: 29a 
spi device id: 1 20 18 3 1 (20180301)
find flash: S25FL128P
raspi_read: from:30000 len:1000 
raspi_read: from:30000 len:1000 
============================================ 
Ralink UBoot Version: 3.6.0.0
-------------------------------------------- 
FPGA 6352_MP (Port5<->Phy)
DRAM_CONF_FROM: From SPI/NAND 
DRAM_TYPE: SDRAM 
DRAM component: 256 Mbits
DRAM bus: 16 bit
Total memory: 32 MBytes
Flash component: SPI Flash
Date:Nov 24 2011  Time:16:21:09
============================================ 
============================================ 
Ralink UBoot Version: 3.6.0.0
-------------------------------------------- 
FPGA 6352_MP (Port5<->Phy)
DRAM_CONF_FROM: From Uboot 
DRAM component: 256 Mbits SDR
DRAM bus: 16 bit
Total memory: 32 MBytes
Flash component: SPI Flash
Date:Nov 24 2011  Time:16:21:09
============================================ 
icache: sets:512, ways:4, linesz:32 ,total:65536
dcache: sets:256, ways:4, linesz:32 ,total:32768 

 ##### The CPU freq = 50 MHZ #### 
 estimate memory size =32 Mbytes
MARVELL Phy1

Please choose the operation: 
   1: Load system code to SDRAM via TFTP. 
   2: Load system code then write to Flash via TFTP. 
   3: Boot system code via Flash (default).
   4: Entr boot command line interface.
   7: Load Boot Loader code then write to Flash via Serial. 
   9: Load Boot Loader code then write to Flash via TFTP. 

You choosed 4

 0 
raspi_read: from:40028 len:6 

   
4: System Enter Boot Command Line Interface.

U-Boot 1.1.3 (Nov 24 2011 - 16:21:09)
RT6352 # msdc card init
[SD0] Bus Width: 1
[SD0] SET_CLK(260kHz): SCLK(255kHz) MODE(0) DDR(0) DIV(47) DS(0) RS(0)
[SD0] SD_SPEC(2) SD_SPEC3(1) SD_BUS_WIDTH=5
[SD0] SD_SECU(2) EX_SECU(0), CMD_SUPP(0): CMD23(0), CMD20(0)
[SD0] Support: Default/SDR12
[SD0] Support: HS/SDR25
[SD0] Support: Type-B Drv
[SD0] Support: 200mA current limit
[SD0] Switch to HS mode!
[SD0] Bus Width: 4
[SD0] Size: 1910 MB, Max.Speed: 50000 kHz, blklen(512), nblks(3911680), ro(0)
[SD0] Initialized
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] Bus Width: 1
[SD0] SET_CLK(260kHz): SCLK(255kHz) MODE(0) DDR(0) DIV(47) DS(0) RS(0)
[SD0] SD_SPEC(2) SD_SPEC3(1) SD_BUS_WIDTH=5
[SD0] SD_SECU(2) EX_SECU(0), CMD_SUPP(0): CMD23(0), CMD20(0)
[SD0] Support: Default/SDR12
[SD0] Support: HS/SDR25
[SD0] Support: Type-B Drv
[SD0] Support: 200mA current limit
[SD0] Switch to HS mode!
[SD0] Bus Width: 4
[SD0] Size: 1910 MB, Max.Speed: 50000 kHz, blklen(512), nblks(3911680), ro(0)
[SD0] Initialized
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] Bus Width: 1
[SD0] SET_CLK(260kHz): SCLK(255kHz) MODE(0) DDR(0) DIV(47) DS(0) RS(0)
[SD0] SD_SPEC(2) SD_SPEC3(1) SD_BUS_WIDTH=5
[SD0] SD_SECU(2) EX_SECU(0), CMD_SUPP(0): CMD23(0), CMD20(0)
[SD0] Support: Default/SDR12
[SD0] Support: HS/SDR25
[SD0] Support: Type-B Drv
[SD0] Support: 200mA current limit
[SD0] Switch to HS mode!
[SD0] Bus Width: 4
[SD0] Size: 1910 MB, Max.Speed: 50000 kHz, blklen(512), nblks(3911680), ro(0)
[SD0] Initialized
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] Bus Width: 1
[SD0] SET_CLK(260kHz): SCLK(255kHz) MODE(0) DDR(0) DIV(47) DS(0) RS(0)
[SD0] SD_SPEC(2) SD_SPEC3(1) SD_BUS_WIDTH=5
[SD0] SD_SECU(2) EX_SECU(0), CMD_SUPP(0): CMD23(0), CMD20(0)
[SD0] Support: Default/SDR12
[SD0] Support: HS/SDR25
[SD0] Support: Type-B Drv
[SD0] Support: 200mA current limit
[SD0] Switch to HS mode!
[SD0] Bus Width: 4
[SD0] Size: 1910 MB, Max.Speed: 50000 kHz, blklen(512), nblks(3911680), ro(0)
[SD0] Initialized
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] Bus Width: 1
[SD0] SET_CLK(260kHz): SCLK(255kHz) MODE(0) DDR(0) DIV(47) DS(0) RS(0)
[SD0] SD_SPEC(2) SD_SPEC3(1) SD_BUS_WIDTH=5
[SD0] SD_SECU(2) EX_SECU(0), CMD_SUPP(0): CMD23(0), CMD20(0)
[SD0] Support: Default/SDR12
[SD0] Support: HS/SDR25
[SD0] Support: Type-B Drv
[SD0] Support: 200mA current limit
[SD0] Switch to HS mode!
[SD0] Bus Width: 4
[SD0] Size: 1910 MB, Max.Speed: 50000 kHz, blklen(512), nblks(3911680), ro(0)
[SD0] Initialized
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
Card Init Test pass!
RT6352 # car   msdc cat rd erase
[SD0] Bus Width: 1
[SD0] SET_CLK(260kHz): SCLK(255kHz) MODE(0) DDR(0) DIV(47) DS(0) RS(0)
[SD0] SD_SPEC(2) SD_SPEC3(1) SD_BUS_WIDTH=5
[SD0] SD_SECU(2) EX_SECU(0), CMD_SUPP(0): CMD23(0), CMD20(0)
[SD0] Support: Default/SDR12
[SD0] Support: HS/SDR25
[SD0] Support: Type-B Drv
[SD0] Support: 200mA current limit
[SD0] Switch to HS mode!
[SD0] Bus Width: 4
[SD0] Size: 1910 MB, Max.Speed: 50000 kHz, blklen(512), nblks(3911680), ro(0)
[SD0] Initialized
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[MSDC0] Erase Addr: 0x8140000 - 0x8148000
[MSDC0] Erasing....
[MSDC0] Erasing....Done

[MSDC0] Erase Addr: 0x8280000 - 0x8288000
[MSDC0] Erasing....
[MSDC0] Erasing....Done

Card Erase Test pass!
RT6352 # msdc card detect
[SD0] Bus Width: 1
[SD0] SET_CLK(260kHz): SCLK(255kHz) MODE(0) DDR(0) DIV(47) DS(0) RS(0)
[SD0] SD_SPEC(2) SD_SPEC3(1) SD_BUS_WIDTH=5
[SD0] SD_SECU(2) EX_SECU(0), CMD_SUPP(0): CMD23(0), CMD20(0)
[SD0] Support: Default/SDR12
[SD0] Support: HS/SDR25
[SD0] Support: Type-B Drv
[SD0] Support: 200mA current limit
[SD0] Switch to HS mode!
[SD0] Bus Width: 4
[SD0] Size: 1910 MB, Max.Speed: 50000 kHz, blklen(512), nblks(3911680), ro(0)
[SD0] Initialized
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[MSDC0] Card inserted(WP=0). Please remove it...[1/5]
[MSDC0] Card removed (WP=0). Please insert it...[2/5]
[SD0] Bus Width: 1
[SD0] SET_CLK(260kHz): SCLK(255kHz) MODE(0) DDR(0) DIV(47) DS(0) RS(0)
[SD0] SD_SPEC(2) SD_SPEC3(1) SD_BUS_WIDTH=5
[SD0] SD_SECU(2) EX_SECU(0), CMD_SUPP(0): CMD23(0), CMD20(0)
[SD0] Support: Default/SDR12
[SD0] Support: HS/SDR25
[SD0] Support: Type-B Drv
[SD0] Support: 200mA current limit
[SD0] Switch to HS mode!
[SD0] Bus Width: 4
[SD0] Size: 1910 MB, Max.Speed: 50000 kHz, blklen(512), nblks(3911680), ro(0)
[SD0] Initialized
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[MSDC0] Card inserted(WP=0). Please remove it...[2/5]
[MSDC0] Card removed (WP=0). Please insert it...[3/5]
[SD0] Bus Width: 1
[SD0] SET_CLK(260kHz): SCLK(255kHz) MODE(0) DDR(0) DIV(47) DS(0) RS(0)
[SD0] SD_SPEC(2) SD_SPEC3(1) SD_BUS_WIDTH=5
[SD0] SD_SECU(2) EX_SECU(0), CMD_SUPP(0): CMD23(0), CMD20(0)
[SD0] Support: Default/SDR12
[SD0] Support: HS/SDR25
[SD0] Support: Type-B Drv
[SD0] Support: 200mA current limit
[SD0] Switch to HS mode!
[SD0] Bus Width: 4
[SD0] Size: 1910 MB, Max.Speed: 50000 kHz, blklen(512), nblks(3911680), ro(0)
[SD0] Initialized
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[MSDC0] Card inserted(WP=0). Please remove it...[3/5]
[MSDC0] Card removed (WP=0). Please insert it...[4/5]
[SD0] Bus Width: 1
[SD0] SET_CLK(260kHz): SCLK(255kHz) MODE(0) DDR(0) DIV(47) DS(0) RS(0)
[SD0] SD_SPEC(2) SD_SPEC3(1) SD_BUS_WIDTH=5
[SD0] SD_SECU(2) EX_SECU(0), CMD_SUPP(0): CMD23(0), CMD20(0)
[SD0] Support: Default/SDR12
[SD0] Support: HS/SDR25
[SD0] Support: Type-B Drv
[SD0] Support: 200mA current limit
[SD0] Switch to HS mode!
[SD0] Bus Width: 4
[SD0] Size: 1910 MB, Max.Speed: 50000 kHz, blklen(512), nblks(3911680), ro(0)
[SD0] Initialized
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[MSDC0] Card inserted(WP=0). Please remove it...[4/5]
[MSDC0] Card removed (WP=0). Please insert it...[5/5]
[SD0] Bus Width: 1
[SD0] SET_CLK(260kHz): SCLK(255kHz) MODE(0) DDR(0) DIV(47) DS(0) RS(0)
[SD0] SD_SPEC(2) SD_SPEC3(1) SD_BUS_WIDTH=5
[SD0] SD_SECU(2) EX_SECU(0), CMD_SUPP(0): CMD23(0), CMD20(0)
[SD0] Support: Default/SDR12
[SD0] Support: HS/SDR25
[SD0] Support: Type-B Drv
[SD0] Support: 200mA current limit
[SD0] Switch to HS mode!
[SD0] Bus Width: 4
[SD0] Size: 1910 MB, Max.Speed: 50000 kHz, blklen(512), nblks(3911680), ro(0)
[SD0] Initialized
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[MSDC0] Card inserted(WP=0). Please remove it...[5/5]
Card Detect Test pass!
RT6352 # msdc blklen
[SD0] Bus Width: 1
[SD0] SET_CLK(260kHz): SCLK(255kHz) MODE(0) DDR(0) DIV(47) DS(0) RS(0)
[SD0] SD_SPEC(2) SD_SPEC3(1) SD_BUS_WIDTH=5
[SD0] SD_SECU(2) EX_SECU(0), CMD_SUPP(0): CMD23(0), CMD20(0)
[SD0] Support: Default/SDR12
[SD0] Support: HS/SDR25
[SD0] Support: Type-B Drv
[SD0] Support: 200mA current limit
[SD0] Switch to HS mode!
[SD0] Bus Width: 4
[SD0] Size: 1910 MB, Max.Speed: 50000 kHz, blklen(512), nblks(3911680), ro(0)
[SD0] Initialized
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] Partial_write:0, Partial_read:1
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] Bus Width: 4
[SD0] 1 bytes Block Size Test
[SD0] 2 bytes Block Size Test
[SD0] 3 bytes Block Size Test
[SD0] 4 bytes Block Size Test
[SD0] 15 bytes Block Size Test
[SD0] 16 bytes Block Size Test
[SD0] 17 bytes Block Size Test
[SD0] 18 bytes Block Size Test
[SD0] 31 bytes Block Size Test
[SD0] 32 bytes Block Size Test
[SD0] 33 bytes Block Size Test
[SD0] 63 bytes Block Size Test
[SD0] 64 bytes Block Size Test
[SD0] 65 bytes Block Size Test
[SD0] 127 bytes Block Size Test
[SD0] 128 bytes Block Size Test
[SD0] 129 bytes Block Size Test
[SD0] 255 bytes Block Size Test
[SD0] 256 bytes Block Size Test
[SD0] 257 bytes Block Size Test
[SD0] 509 bytes Block Size Test
[SD0] 510 bytes Block Size Test
[SD0] 511 bytes Block Size Test
[SD0] 512 bytes Block Size Test
[SD0] SW=0, SR=0, MW=0, MR=0, Blksz=1
[SD0] SW=0, SR=0, MW=0, MR=0, Blksz=2
[SD0] SW=0, SR=0, MW=0, MR=0, Blksz=3
[SD0] SW=0, SR=0, MW=0, MR=0, Blksz=4
[SD0] SW=0, SR=0, MW=0, MR=0, Blksz=15
[SD0] SW=0, SR=0, MW=0, MR=0, Blksz=16
[SD0] SW=0, SR=0, MW=0, MR=0, Blksz=17
[SD0] SW=0, SR=0, MW=0, MR=0, Blksz=18
[SD0] SW=0, SR=0, MW=0, MR=0, Blksz=31
[SD0] SW=0, SR=0, MW=0, MR=0, Blksz=32
[SD0] SW=0, SR=0, MW=0, MR=0, Blksz=33
[SD0] SW=0, SR=0, MW=0, MR=0, Blksz=63
[SD0] SW=0, SR=0, MW=0, MR=0, Blksz=64
[SD0] SW=0, SR=0, MW=0, MR=0, Blksz=65
[SD0] SW=0, SR=0, MW=0, MR=0, Blksz=127
[SD0] SW=0, SR=0, MW=0, MR=0, Blksz=128
[SD0] SW=0, SR=0, MW=0, MR=0, Blksz=129
[SD0] SW=0, SR=0, MW=0, MR=0, Blksz=255
[SD0] SW=0, SR=0, MW=0, MR=0, Blksz=256
[SD0] SW=0, SR=0, MW=0, MR=0, Blksz=257
[SD0] SW=0, SR=0, MW=0, MR=0, Blksz=509
[SD0] SW=0, SR=0, MW=0, MR=0, Blksz=510
[SD0] SW=0, SR=0, MW=0, MR=0, Blksz=511
[SD0] SW=0, SR=0, MW=0, MR=0, Blksz=512
Block Length Test pass!
RT6352 # msdc pio
[TST] ==============================================
[TST] BEGIN: 1/1, No Stop(0)
[TST] ----------------------------------------------
[TST] Mode    : 1
[TST] Clock   : 48000 kHz
[TST] BusWidth: 4 bits
[TST] BurstSz : 64 bytes
[TST] BlkAddr : 40000h
[TST] BlkSize : 512bytes
[TST] TstBlks : 256
[TST] AutoCMD : 12(0), 23(0)
[TST] ----------------------------------------------
[SD0] Bus Width: 1
[SD0] SET_CLK(260kHz): SCLK(255kHz) MODE(0) DDR(0) DIV(47) DS(0) RS(0)
[SD0] SD_SPEC(2) SD_SPEC3(1) SD_BUS_WIDTH=5
[SD0] SD_SECU(2) EX_SECU(0), CMD_SUPP(0): CMD23(0), CMD20(0)
[SD0] Support: Default/SDR12
[SD0] Support: HS/SDR25
[SD0] Support: Type-B Drv
[SD0] Support: 200mA current limit
[SD0] Switch to HS mode!
[SD0] Bus Width: 4
[SD0] Size: 1910 MB, Max.Speed: 50000 kHz, blklen(512), nblks(3911680), ro(0)
[SD0] Initialized
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] Bus Width: 4
[TST] PIO bits: 32
[TST] 0x8000000 - 0x8020000 Erased
[SD0] <PASS> TC0: test single block write
[SD0] <PASS> TC1: test single block read
[SD0] <PASS> TC2: test multiple block write
[SD0] <PASS> TC3: test multiple block read
[SD0] <PASS> TC4: test multiple block interleave write-read
[TST] ----------------------------------------------
[TST] Report -  PIO R/W Test 
[TST] ----------------------------------------------
[TST] ----------------------------------------------
[TST] Test Result: TOTAL(1/1), PASS(1), FAIL(0) 
[TST] ----------------------------------------------
[TST] ==============================================
[TST] BEGIN: 1/1, No Stop(0)
[TST] ----------------------------------------------
[TST] Mode    : 1
[TST] Clock   : 48000 kHz
[TST] BusWidth: 4 bits
[TST] BurstSz : 64 bytes
[TST] BlkAddr : 40000h
[TST] BlkSize : 512bytes
[TST] TstBlks : 256
[TST] AutoCMD : 12(0), 23(0)
[TST] ----------------------------------------------
[SD0] Bus Width: 1
[SD0] SET_CLK(260kHz): SCLK(255kHz) MODE(0) DDR(0) DIV(47) DS(0) RS(0)
[SD0] SD_SPEC(2) SD_SPEC3(1) SD_BUS_WIDTH=5
[SD0] SD_SECU(2) EX_SECU(0), CMD_SUPP(0): CMD23(0), CMD20(0)
[SD0] Support: Default/SDR12
[SD0] Support: HS/SDR25
[SD0] Support: Type-B Drv
[SD0] Support: 200mA current limit
[SD0] Switch to HS mode!
[SD0] Bus Width: 4
[SD0] Size: 1910 MB, Max.Speed: 50000 kHz, blklen(512), nblks(3911680), ro(0)
[SD0] Initialized
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] Bus Width: 4
[TST] PIO bits: 16
[TST] 0x8000000 - 0x8020000 Erased
[SD0] <PASS> TC0: test single block write
[SD0] <PASS> TC1: test single block read
[SD0] <PASS> TC2: test multiple block write
[SD0] <PASS> TC3: test multiple block read
[SD0] <PASS> TC4: test multiple block interleave write-read
[TST] ----------------------------------------------
[TST] Report -  PIO R/W Test 
[TST] ----------------------------------------------
[TST] ----------------------------------------------
[TST] Test Result: TOTAL(1/1), PASS(1), FAIL(0) 
[TST] ----------------------------------------------
[TST] ==============================================
[TST] BEGIN: 1/1, No Stop(0)
[TST] ----------------------------------------------
[TST] Mode    : 1
[TST] Clock   : 48000 kHz
[TST] BusWidth: 4 bits
[TST] BurstSz : 64 bytes
[TST] BlkAddr : 40000h
[TST] BlkSize : 512bytes
[TST] TstBlks : 256
[TST] AutoCMD : 12(0), 23(0)
[TST] ----------------------------------------------
[SD0] Bus Width: 1
[SD0] SET_CLK(260kHz): SCLK(255kHz) MODE(0) DDR(0) DIV(47) DS(0) RS(0)
[SD0] SD_SPEC(2) SD_SPEC3(1) SD_BUS_WIDTH=5
[SD0] SD_SECU(2) EX_SECU(0), CMD_SUPP(0): CMD23(0), CMD20(0)
[SD0] Support: Default/SDR12
[SD0] Support: HS/SDR25
[SD0] Support: Type-B Drv
[SD0] Support: 200mA current limit
[SD0] Switch to HS mode!
[SD0] Bus Width: 4
[SD0] Size: 1910 MB, Max.Speed: 50000 kHz, blklen(512), nblks(3911680), ro(0)
[SD0] Initialized
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] Bus Width: 4
[TST] PIO bits: 8
[TST] 0x8000000 - 0x8020000 Erased
[SD0] <PASS> TC0: test single block write
[SD0] <PASS> TC1: test single block read
[SD0] <PASS> TC2: test multiple block write
[SD0] <PASS> TC3: test multiple block read
[SD0] <PASS> TC4: test multiple block interleave write-read
[TST] ----------------------------------------------
[TST] Report -  PIO R/W Test 
[TST] ----------------------------------------------
[TST] ----------------------------------------------
[TST] Test Result: TOTAL(1/1), PASS(1), FAIL(0) 
[TST] ----------------------------------------------
PIO Test pass!
RT6352 # msdc dma basic
[TST] ==============================================
[TST] BEGIN: 1/1, No Stop(0)
[TST] ----------------------------------------------
[TST] Mode    : 2
[TST] Clock   : 48000 kHz
[TST] BusWidth: 4 bits
[TST] BurstSz : 64 bytes
[TST] BlkAddr : 40000h
[TST] BlkSize : 512bytes
[TST] TstBlks : 256
[TST] AutoCMD : 12(0), 23(0)
[TST] ----------------------------------------------
[SD0] Bus Width: 1
[SD0] SET_CLK(260kHz): SCLK(255kHz) MODE(0) DDR(0) DIV(47) DS(0) RS(0)
[SD0] SD_SPEC(2) SD_SPEC3(1) SD_BUS_WIDTH=5
[SD0] SD_SECU(2) EX_SECU(0), CMD_SUPP(0): CMD23(0), CMD20(0)
[SD0] Support: Default/SDR12
[SD0] Support: HS/SDR25
[SD0] Support: Type-B Drv
[SD0] Support: 200mA current limit
[SD0] Switch to HS mode!
[SD0] Bus Width: 4
[SD0] Size: 1910 MB, Max.Speed: 50000 kHz, blklen(512), nblks(3911680), ro(0)
[SD0] Initialized
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] Bus Width: 4
[TST] 0x8000000 - 0x8020000 Erased
[SD0] <PASS> TC0: test single block write
[SD0] <PASS> TC1: test single block read
[SD0] <PASS> TC2: test multiple block write
[SD0] <PASS> TC3: test multiple block read
[SD0] <PASS> TC4: test multiple block interleave write-read
[TST] ----------------------------------------------
[TST] Report -  Basic DMA R/W Test 
[TST] ----------------------------------------------
[TST] ----------------------------------------------
[TST] Test Result: TOTAL(1/1), PASS(1), FAIL(0) 
[TST] ----------------------------------------------
Basic DMA Test pass!
RT6352 # msdc dma desc
[TST] ==============================================
[TST] BEGIN: 1/1, No Stop(0)
[TST] ----------------------------------------------
[TST] Mode    : 3
[TST] Clock   : 48000 kHz
[TST] BusWidth: 4 bits
[TST] BurstSz : 64 bytes
[TST] BlkAddr : 40000h
[TST] BlkSize : 512bytes
[TST] TstBlks : 256
[TST] AutoCMD : 12(0), 23(0)
[TST] ----------------------------------------------
[SD0] Bus Width: 1
[SD0] SET_CLK(260kHz): SCLK(255kHz) MODE(0) DDR(0) DIV(47) DS(0) RS(0)
[SD0] SD_SPEC(2) SD_SPEC3(1) SD_BUS_WIDTH=5
[SD0] SD_SECU(2) EX_SECU(0), CMD_SUPP(0): CMD23(0), CMD20(0)
[SD0] Support: Default/SDR12
[SD0] Support: HS/SDR25
[SD0] Support: Type-B Drv
[SD0] Support: 200mA current limit
[SD0] Switch to HS mode!
[SD0] Bus Width: 4
[SD0] Size: 1910 MB, Max.Speed: 50000 kHz, blklen(512), nblks(3911680), ro(0)
[SD0] Initialized
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] Bus Width: 4
[TST] 0x8000000 - 0x8020000 Erased
[SD0] <PASS> TC0: test single block write
[SD0] <PASS> TC1: test single block read
[SD0] <PASS> TC2: test multiple block write
[SD0] <PASS> TC3: test multiple block read
[SD0] <PASS> TC4: test multiple block interleave write-read
[TST] ----------------------------------------------
[TST] Report -  Desc. DMA R/W Test 
[TST] ----------------------------------------------
[TST] ----------------------------------------------
[TST] Test Result: TOTAL(1/1), PASS(1), FAIL(0) 
[TST] ----------------------------------------------
[TST] ==============================================
[TST] BEGIN: 1/1, No Stop(0)
[TST] ----------------------------------------------
[TST] Mode    : 3
[TST] Clock   : 48000 kHz
[TST] BusWidth: 4 bits
[TST] BurstSz : 64 bytes
[TST] BlkAddr : 40000h
[TST] BlkSize : 512bytes
[TST] TstBlks : 256
[TST] AutoCMD : 12(0), 23(0)
[TST] ----------------------------------------------
[SD0] Bus Width: 1
[SD0] SET_CLK(260kHz): SCLK(255kHz) MODE(0) DDR(0) DIV(47) DS(0) RS(0)
[SD0] SD_SPEC(2) SD_SPEC3(1) SD_BUS_WIDTH=5
[SD0] SD_SECU(2) EX_SECU(0), CMD_SUPP(0): CMD23(0), CMD20(0)
[SD0] Support: Default/SDR12
[SD0] Support: HS/SDR25
[SD0] Support: Type-B Drv
[SD0] Support: 200mA current limit
[SD0] Switch to HS mode!
[SD0] Bus Width: 4
[SD0] Size: 1910 MB, Max.Speed: 50000 kHz, blklen(512), nblks(3911680), ro(0)
[SD0] Initialized
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] Bus Width: 4
[TST] 0x8000000 - 0x8020000 Erased
[SD0] <PASS> TC0: test single block write
[SD0] <PASS> TC1: test single block read
[SD0] <PASS> TC2: test multiple block write
[SD0] <PASS> TC3: test multiple block read
[SD0] <PASS> TC4: test multiple block interleave write-read
[TST] ----------------------------------------------
[TST] Report -  Desc. DMA R/W Test 
[TST] ----------------------------------------------
[TST] ----------------------------------------------
[TST] Test Result: TOTAL(1/1), PASS(1), FAIL(0) 
[TST] ----------------------------------------------
Desc. DMA Test pass!
RT6352 # msdc dma enhance
[TST] ==============================================
[TST] BEGIN: 1/1, No Stop(0)
[TST] ----------------------------------------------
[TST] Mode    : 4
[TST] Clock   : 48000 kHz
[TST] BusWidth: 4 bits
[TST] BurstSz : 64 bytes
[TST] BlkAddr : 40000h
[TST] BlkSize : 512bytes
[TST] TstBlks : 256
[TST] AutoCMD : 12(0), 23(0)
[TST] ----------------------------------------------
[SD0] Bus Width: 1
[SD0] SET_CLK(260kHz): SCLK(255kHz) MODE(0) DDR(0) DIV(47) DS(0) RS(0)
[SD0] SD_SPEC(2) SD_SPEC3(1) SD_BUS_WIDTH=5
[SD0] SD_SECU(2) EX_SECU(0), CMD_SUPP(0): CMD23(0), CMD20(0)
[SD0] Support: Default/SDR12
[SD0] Support: HS/SDR25
[SD0] Support: Type-B Drv
[SD0] Support: 200mA current limit
[SD0] Switch to HS mode!
[SD0] Bus Width: 4
[SD0] Size: 1910 MB, Max.Speed: 50000 kHz, blklen(512), nblks(3911680), ro(0)
[SD0] Initialized
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] Bus Width: 4
[TST] 0x8000000 - 0x8020000 Erased
[SD0] <PASS> TC0: test single block write
[SD0] <PASS> TC1: test single block read
[SD0] <PASS> TC2: test multiple block write
[SD0] <PASS> TC3: test multiple block read
[SD0] <PASS> TC4: test multiple block interleave write-read
[TST] ----------------------------------------------
[TST] Report -  Enhanced DMA R/W Test 
[TST] ----------------------------------------------
[TST] ----------------------------------------------
[TST] Test Result: TOTAL(1/1), PASS(1), FAIL(0) 
[TST] ----------------------------------------------
[TST] ==============================================
[TST] BEGIN: 1/1, No Stop(0)
[TST] ----------------------------------------------
[TST] Mode    : 4
[TST] Clock   : 48000 kHz
[TST] BusWidth: 4 bits
[TST] BurstSz : 64 bytes
[TST] BlkAddr : 40000h
[TST] BlkSize : 512bytes
[TST] TstBlks : 256
[TST] AutoCMD : 12(0), 23(0)
[TST] ----------------------------------------------
[SD0] Bus Width: 1
[SD0] SET_CLK(260kHz): SCLK(255kHz) MODE(0) DDR(0) DIV(47) DS(0) RS(0)
[SD0] SD_SPEC(2) SD_SPEC3(1) SD_BUS_WIDTH=5
[SD0] SD_SECU(2) EX_SECU(0), CMD_SUPP(0): CMD23(0), CMD20(0)
[SD0] Support: Default/SDR12
[SD0] Support: HS/SDR25
[SD0] Support: Type-B Drv
[SD0] Support: 200mA current limit
[SD0] Switch to HS mode!
[SD0] Bus Width: 4
[SD0] Size: 1910 MB, Max.Speed: 50000 kHz, blklen(512), nblks(3911680), ro(0)
[SD0] Initialized
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] Bus Width: 4
[TST] 0x8000000 - 0x8020000 Erased
[SD0] <PASS> TC0: test single block write
[SD0] <PASS> TC1: test single block read
[SD0] <PASS> TC2: test multiple block write
[SD0] <PASS> TC3: test multiple block read
[SD0] <PASS> TC4: test multiple block interleave write-read
[TST] ----------------------------------------------
[TST] Report -  Enhanced DMA R/W Test 
[TST] ----------------------------------------------
[TST] ----------------------------------------------
[TST] Test Result: TOTAL(1/1), PASS(1), FAIL(0) 
[TST] ----------------------------------------------
Enhance DMA Test pass!
RT6352 # msdc cm, d12
[TST] ==============================================
[TST] BEGIN: 1/1, No Stop(0)
[TST] ----------------------------------------------
[TST] Mode    : 2
[TST] Clock   : 48000 kHz
[TST] BusWidth: 4 bits
[TST] BurstSz : 64 bytes
[TST] BlkAddr : 40000h
[TST] BlkSize : 512bytes
[TST] TstBlks : 256
[TST] AutoCMD : 12(1), 23(0)
[TST] ----------------------------------------------
[SD0] Bus Width: 1
[SD0] SET_CLK(260kHz): SCLK(255kHz) MODE(0) DDR(0) DIV(47) DS(0) RS(0)
[SD0] SD_SPEC(2) SD_SPEC3(1) SD_BUS_WIDTH=5
[SD0] SD_SECU(2) EX_SECU(0), CMD_SUPP(0): CMD23(0), CMD20(0)
[SD0] Support: Default/SDR12
[SD0] Support: HS/SDR25
[SD0] Support: Type-B Drv
[SD0] Support: 200mA current limit
[SD0] Switch to HS mode!
[SD0] Bus Width: 4
[SD0] Size: 1910 MB, Max.Speed: 50000 kHz, blklen(512), nblks(3911680), ro(0)
[SD0] Initialized
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] Bus Width: 4
[TST] 0x8000000 - 0x8020000 Erased
[SD0] <PASS> TC0: test single block write
[SD0] <PASS> TC1: test single block read
[SD0] <PASS> TC2: test multiple block write
[SD0] <PASS> TC3: test multiple block read
[SD0] <PASS> TC4: test multiple block interleave write-read
[TST] ----------------------------------------------
[TST] Report -  Auto CMD12 Test 
[TST] ----------------------------------------------
[TST] ----------------------------------------------
[TST] Test Result: TOTAL(1/1), PASS(1), FAIL(0) 
[TST] ----------------------------------------------
[TST] ==============================================
[TST] BEGIN: 1/1, No Stop(0)
[TST] ----------------------------------------------
[TST] Mode    : 3
[TST] Clock   : 48000 kHz
[TST] BusWidth: 4 bits
[TST] BurstSz : 64 bytes
[TST] BlkAddr : 40000h
[TST] BlkSize : 512bytes
[TST] TstBlks : 256
[TST] AutoCMD : 12(1), 23(0)
[TST] ----------------------------------------------
[SD0] Bus Width: 1
[SD0] SET_CLK(260kHz): SCLK(255kHz) MODE(0) DDR(0) DIV(47) DS(0) RS(0)
[SD0] SD_SPEC(2) SD_SPEC3(1) SD_BUS_WIDTH=5
[SD0] SD_SECU(2) EX_SECU(0), CMD_SUPP(0): CMD23(0), CMD20(0)
[SD0] Support: Default/SDR12
[SD0] Support: HS/SDR25
[SD0] Support: Type-B Drv
[SD0] Support: 200mA current limit
[SD0] Switch to HS mode!
[SD0] Bus Width: 4
[SD0] Size: 1910 MB, Max.Speed: 50000 kHz, blklen(512), nblks(3911680), ro(0)
[SD0] Initialized
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] Bus Width: 4
[TST] 0x8000000 - 0x8020000 Erased
[SD0] <PASS> TC0: test single block write
[SD0] <PASS> TC1: test single block read
[SD0] <PASS> TC2: test multiple block write
[SD0] <PASS> TC3: test multiple block read
[SD0] <PASS> TC4: test multiple block interleave write-read
[TST] ----------------------------------------------
[TST] Report -  Auto CMD12 Test 
[TST] ----------------------------------------------
[TST] ----------------------------------------------
[TST] Test Result: TOTAL(1/1), PASS(1), FAIL(0) 
[TST] ----------------------------------------------
[TST] ==============================================
[TST] BEGIN: 1/1, No Stop(0)
[TST] ----------------------------------------------
[TST] Mode    : 4
[TST] Clock   : 48000 kHz
[TST] BusWidth: 4 bits
[TST] BurstSz : 64 bytes
[TST] BlkAddr : 40000h
[TST] BlkSize : 512bytes
[TST] TstBlks : 256
[TST] AutoCMD : 12(1), 23(0)
[TST] ----------------------------------------------
[SD0] Bus Width: 1
[SD0] SET_CLK(260kHz): SCLK(255kHz) MODE(0) DDR(0) DIV(47) DS(0) RS(0)
[SD0] SD_SPEC(2) SD_SPEC3(1) SD_BUS_WIDTH=5
[SD0] SD_SECU(2) EX_SECU(0), CMD_SUPP(0): CMD23(0), CMD20(0)
[SD0] Support: Default/SDR12
[SD0] Support: HS/SDR25
[SD0] Support: Type-B Drv
[SD0] Support: 200mA current limit
[SD0] Switch to HS mode!
[SD0] Bus Width: 4
[SD0] Size: 1910 MB, Max.Speed: 50000 kHz, blklen(512), nblks(3911680), ro(0)
[SD0] Initialized
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] Bus Width: 4
[TST] 0x8000000 - 0x8020000 Erased
[SD0] <PASS> TC0: test single block write
[SD0] <PASS> TC1: test single block read
[SD0] <PASS> TC2: test multiple block write
[SD0] <PASS> TC3: test multiple block read
[SD0] <PASS> TC4: test multiple block interleave write-read
[TST] ----------------------------------------------
[TST] Report -  Auto CMD12 Test 
[TST] ----------------------------------------------
[TST] ----------------------------------------------
[TST] Test Result: TOTAL(1/1), PASS(1), FAIL(0) 
[TST] ----------------------------------------------
Auto Command 12 Test pass!
RT6352 # msdc stress
[SD0] Bus Width: 1
[SD0] SET_CLK(260kHz): SCLK(255kHz) MODE(0) DDR(0) DIV(47) DS(0) RS(0)
[SD0] SD_SPEC(2) SD_SPEC3(1) SD_BUS_WIDTH=5
[SD0] SD_SECU(2) EX_SECU(0), CMD_SUPP(0): CMD23(0), CMD20(0)
[SD0] Support: Default/SDR12
[SD0] Support: HS/SDR25
[SD0] Support: Type-B Drv
[SD0] Support: 200mA current limit
[SD0] Switch to HS mode!
[SD0] Bus Width: 4
[SD0] Size: 1910 MB, Max.Speed: 50000 kHz, blklen(512), nblks(3911680), ro(0)
[SD0] Initialized
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] Bus Width: 1
[SD0] SET_CLK(260kHz): SCLK(255kHz) MODE(0) DDR(0) DIV(47) DS(0) RS(0)
[SD0] SD_SPEC(2) SD_SPEC3(1) SD_BUS_WIDTH=5
[SD0] SD_SECU(2) EX_SECU(0), CMD_SUPP(0): CMD23(0), CMD20(0)
[SD0] Support: Default/SDR12
[SD0] Support: HS/SDR25
[SD0] Support: Type-B Drv
[SD0] Support: 200mA current limit
[SD0] Switch to HS mode!
[SD0] Bus Width: 4
[SD0] Size: 1910 MB, Max.Speed: 50000 kHz, blklen(512), nblks(3911680), ro(0)
[SD0] Initialized
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] Bus Width: 1
[SD0] SET_CLK(260kHz): SCLK(255kHz) MODE(0) DDR(0) DIV(47) DS(0) RS(0)
[SD0] SD_SPEC(2) SD_SPEC3(1) SD_BUS_WIDTH=5
[SD0] SD_SECU(2) EX_SECU(0), CMD_SUPP(0): CMD23(0), CMD20(0)
[SD0] Support: Default/SDR12
[SD0] Support: HS/SDR25
[SD0] Support: Type-B Drv
[SD0] Support: 200mA current limit
[SD0] Switch to HS mode!
[SD0] Bus Width: 4
[SD0] Size: 1910 MB, Max.Speed: 50000 kHz, blklen(512), nblks(3911680), ro(0)
[SD0] Initialized
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] Bus Width: 1
[SD0] SET_CLK(260kHz): SCLK(255kHz) MODE(0) DDR(0) DIV(47) DS(0) RS(0)
[SD0] SD_SPEC(2) SD_SPEC3(1) SD_BUS_WIDTH=5
[SD0] SD_SECU(2) EX_SECU(0), CMD_SUPP(0): CMD23(0), CMD20(0)
[SD0] Support: Default/SDR12
[SD0] Support: HS/SDR25
[SD0] Support: Type-B Drv
[SD0] Support: 200mA current limit
[SD0] Switch to HS mode!
[SD0] Bus Width: 4
[SD0] Size: 1910 MB, Max.Speed: 50000 kHz, blklen(512), nblks(3911680), ro(0)
[SD0] Initialized
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] Bus Width: 1
[SD0] SET_CLK(260kHz): SCLK(255kHz) MODE(0) DDR(0) DIV(47) DS(0) RS(0)
[SD0] SD_SPEC(2) SD_SPEC3(1) SD_BUS_WIDTH=5
[SD0] SD_SECU(2) EX_SECU(0), CMD_SUPP(0): CMD23(0), CMD20(0)
[SD0] Support: Default/SDR12
[SD0] Support: HS/SDR25
[SD0] Support: Type-B Drv
[SD0] Support: 200mA current limit
[SD0] Switch to HS mode!
[SD0] Bus Width: 4
[SD0] Size: 1910 MB, Max.Speed: 50000 kHz, blklen(512), nblks(3911680), ro(0)
[SD0] Initialized
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
Card Init Test pass!
[SD0] Bus Width: 1
[SD0] SET_CLK(260kHz): SCLK(255kHz) MODE(0) DDR(0) DIV(47) DS(0) RS(0)
[SD0] SD_SPEC(2) SD_SPEC3(1) SD_BUS_WIDTH=5
[SD0] SD_SECU(2) EX_SECU(0), CMD_SUPP(0): CMD23(0), CMD20(0)
[SD0] Support: Default/SDR12
[SD0] Support: HS/SDR25
[SD0] Support: Type-B Drv
[SD0] Support: 200mA current limit
[SD0] Switch to HS mode!
[SD0] Bus Width: 4
[SD0] Size: 1910 MB, Max.Speed: 50000 kHz, blklen(512), nblks(3911680), ro(0)
[SD0] Initialized
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[MSDC0] Erase Addr: 0x8140000 - 0x8148000
[MSDC0] Erasing....
[MSDC0] Erasing....Done

[MSDC0] Erase Addr: 0x8280000 - 0x8288000
[MSDC0] Erasing....
[MSDC0] Erasing....Done

Card Erase Test pass!
[TST] ==============================================
[TST] BEGIN: 1/1, No Stop(0)
[TST] ----------------------------------------------
[TST] Mode    : 1
[TST] Clock   : 48000 kHz
[TST] BusWidth: 4 bits
[TST] BurstSz : 64 bytes
[TST] BlkAddr : 40000h
[TST] BlkSize : 512bytes
[TST] TstBlks : 256
[TST] AutoCMD : 12(0), 23(0)
[TST] ----------------------------------------------
[SD0] Bus Width: 1
[SD0] SET_CLK(260kHz): SCLK(255kHz) MODE(0) DDR(0) DIV(47) DS(0) RS(0)
[SD0] SD_SPEC(2) SD_SPEC3(1) SD_BUS_WIDTH=5
[SD0] SD_SECU(2) EX_SECU(0), CMD_SUPP(0): CMD23(0), CMD20(0)
[SD0] Support: Default/SDR12
[SD0] Support: HS/SDR25
[SD0] Support: Type-B Drv
[SD0] Support: 200mA current limit
[SD0] Switch to HS mode!
[SD0] Bus Width: 4
[SD0] Size: 1910 MB, Max.Speed: 50000 kHz, blklen(512), nblks(3911680), ro(0)
[SD0] Initialized
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] Bus Width: 4
[TST] PIO bits: 32
[TST] 0x8000000 - 0x8020000 Erased
[SD0] <PASS> TC0: test single block write
[SD0] <PASS> TC1: test single block read
[SD0] <PASS> TC2: test multiple block write
[SD0] <PASS> TC3: test multiple block read
[SD0] <PASS> TC4: test multiple block interleave write-read
[TST] ----------------------------------------------
[TST] Report -  PIO R/W Test 
[TST] ----------------------------------------------
[TST] ----------------------------------------------
[TST] Test Result: TOTAL(1/1), PASS(1), FAIL(0) 
[TST] ----------------------------------------------
[TST] ==============================================
[TST] BEGIN: 1/1, No Stop(0)
[TST] ----------------------------------------------
[TST] Mode    : 1
[TST] Clock   : 48000 kHz
[TST] BusWidth: 4 bits
[TST] BurstSz : 64 bytes
[TST] BlkAddr : 40000h
[TST] BlkSize : 512bytes
[TST] TstBlks : 256
[TST] AutoCMD : 12(0), 23(0)
[TST] ----------------------------------------------
[SD0] Bus Width: 1
[SD0] SET_CLK(260kHz): SCLK(255kHz) MODE(0) DDR(0) DIV(47) DS(0) RS(0)
[SD0] SD_SPEC(2) SD_SPEC3(1) SD_BUS_WIDTH=5
[SD0] SD_SECU(2) EX_SECU(0), CMD_SUPP(0): CMD23(0), CMD20(0)
[SD0] Support: Default/SDR12
[SD0] Support: HS/SDR25
[SD0] Support: Type-B Drv
[SD0] Support: 200mA current limit
[SD0] Switch to HS mode!
[SD0] Bus Width: 4
[SD0] Size: 1910 MB, Max.Speed: 50000 kHz, blklen(512), nblks(3911680), ro(0)
[SD0] Initialized
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] Bus Width: 4
[TST] PIO bits: 16
[TST] 0x8000000 - 0x8020000 Erased
[SD0] <PASS> TC0: test single block write
[SD0] <PASS> TC1: test single block read
[SD0] <PASS> TC2: test multiple block write
[SD0] <PASS> TC3: test multiple block read
[SD0] <PASS> TC4: test multiple block interleave write-read
[TST] ----------------------------------------------
[TST] Report -  PIO R/W Test 
[TST] ----------------------------------------------
[TST] ----------------------------------------------
[TST] Test Result: TOTAL(1/1), PASS(1), FAIL(0) 
[TST] ----------------------------------------------
[TST] ==============================================
[TST] BEGIN: 1/1, No Stop(0)
[TST] ----------------------------------------------
[TST] Mode    : 1
[TST] Clock   : 48000 kHz
[TST] BusWidth: 4 bits
[TST] BurstSz : 64 bytes
[TST] BlkAddr : 40000h
[TST] BlkSize : 512bytes
[TST] TstBlks : 256
[TST] AutoCMD : 12(0), 23(0)
[TST] ----------------------------------------------
[SD0] Bus Width: 1
[SD0] SET_CLK(260kHz): SCLK(255kHz) MODE(0) DDR(0) DIV(47) DS(0) RS(0)
[SD0] SD_SPEC(2) SD_SPEC3(1) SD_BUS_WIDTH=5
[SD0] SD_SECU(2) EX_SECU(0), CMD_SUPP(0): CMD23(0), CMD20(0)
[SD0] Support: Default/SDR12
[SD0] Support: HS/SDR25
[SD0] Support: Type-B Drv
[SD0] Support: 200mA current limit
[SD0] Switch to HS mode!
[SD0] Bus Width: 4
[SD0] Size: 1910 MB, Max.Speed: 50000 kHz, blklen(512), nblks(3911680), ro(0)
[SD0] Initialized
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] Bus Width: 4
[TST] PIO bits: 8
[TST] 0x8000000 - 0x8020000 Erased
[SD0] <PASS> TC0: test single block write
[SD0] <PASS> TC1: test single block read
[SD0] <PASS> TC2: test multiple block write
[SD0] <PASS> TC3: test multiple block read
[SD0] <PASS> TC4: test multiple block interleave write-read
[TST] ----------------------------------------------
[TST] Report -  PIO R/W Test 
[TST] ----------------------------------------------
[TST] ----------------------------------------------
[TST] Test Result: TOTAL(1/1), PASS(1), FAIL(0) 
[TST] ----------------------------------------------
PIO Test pass!
[TST] ==============================================
[TST] BEGIN: 1/1, No Stop(0)
[TST] ----------------------------------------------
[TST] Mode    : 2
[TST] Clock   : 48000 kHz
[TST] BusWidth: 4 bits
[TST] BurstSz : 64 bytes
[TST] BlkAddr : 40000h
[TST] BlkSize : 512bytes
[TST] TstBlks : 256
[TST] AutoCMD : 12(0), 23(0)
[TST] ----------------------------------------------
[SD0] Bus Width: 1
[SD0] SET_CLK(260kHz): SCLK(255kHz) MODE(0) DDR(0) DIV(47) DS(0) RS(0)
[SD0] SD_SPEC(2) SD_SPEC3(1) SD_BUS_WIDTH=5
[SD0] SD_SECU(2) EX_SECU(0), CMD_SUPP(0): CMD23(0), CMD20(0)
[SD0] Support: Default/SDR12
[SD0] Support: HS/SDR25
[SD0] Support: Type-B Drv
[SD0] Support: 200mA current limit
[SD0] Switch to HS mode!
[SD0] Bus Width: 4
[SD0] Size: 1910 MB, Max.Speed: 50000 kHz, blklen(512), nblks(3911680), ro(0)
[SD0] Initialized
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] Bus Width: 4
[TST] 0x8000000 - 0x8020000 Erased
[SD0] <PASS> TC0: test single block write
[SD0] <PASS> TC1: test single block read
[SD0] <PASS> TC2: test multiple block write
[SD0] <PASS> TC3: test multiple block read
[SD0] <PASS> TC4: test multiple block interleave write-read
[TST] ----------------------------------------------
[TST] Report -  Basic DMA R/W Test 
[TST] ----------------------------------------------
[TST] ----------------------------------------------
[TST] Test Result: TOTAL(1/1), PASS(1), FAIL(0) 
[TST] ----------------------------------------------
Basic DMA Test pass!
[TST] ==============================================
[TST] BEGIN: 1/1, No Stop(0)
[TST] ----------------------------------------------
[TST] Mode    : 3
[TST] Clock   : 48000 kHz
[TST] BusWidth: 4 bits
[TST] BurstSz : 64 bytes
[TST] BlkAddr : 40000h
[TST] BlkSize : 512bytes
[TST] TstBlks : 256
[TST] AutoCMD : 12(0), 23(0)
[TST] ----------------------------------------------
[SD0] Bus Width: 1
[SD0] SET_CLK(260kHz): SCLK(255kHz) MODE(0) DDR(0) DIV(47) DS(0) RS(0)
[SD0] SD_SPEC(2) SD_SPEC3(1) SD_BUS_WIDTH=5
[SD0] SD_SECU(2) EX_SECU(0), CMD_SUPP(0): CMD23(0), CMD20(0)
[SD0] Support: Default/SDR12
[SD0] Support: HS/SDR25
[SD0] Support: Type-B Drv
[SD0] Support: 200mA current limit
[SD0] Switch to HS mode!
[SD0] Bus Width: 4
[SD0] Size: 1910 MB, Max.Speed: 50000 kHz, blklen(512), nblks(3911680), ro(0)
[SD0] Initialized
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] Bus Width: 4
[TST] 0x8000000 - 0x8020000 Erased
[SD0] <PASS> TC0: test single block write
[SD0] <PASS> TC1: test single block read
[SD0] <PASS> TC2: test multiple block write
[SD0] <PASS> TC3: test multiple block read
[SD0] <PASS> TC4: test multiple block interleave write-read
[TST] ----------------------------------------------
[TST] Report -  Desc. DMA R/W Test 
[TST] ----------------------------------------------
[TST] ----------------------------------------------
[TST] Test Result: TOTAL(1/1), PASS(1), FAIL(0) 
[TST] ----------------------------------------------
[TST] ==============================================
[TST] BEGIN: 1/1, No Stop(0)
[TST] ----------------------------------------------
[TST] Mode    : 3
[TST] Clock   : 48000 kHz
[TST] BusWidth: 4 bits
[TST] BurstSz : 64 bytes
[TST] BlkAddr : 40000h
[TST] BlkSize : 512bytes
[TST] TstBlks : 256
[TST] AutoCMD : 12(0), 23(0)
[TST] ----------------------------------------------
[SD0] Bus Width: 1
[SD0] SET_CLK(260kHz): SCLK(255kHz) MODE(0) DDR(0) DIV(47) DS(0) RS(0)
[SD0] SD_SPEC(2) SD_SPEC3(1) SD_BUS_WIDTH=5
[SD0] SD_SECU(2) EX_SECU(0), CMD_SUPP(0): CMD23(0), CMD20(0)
[SD0] Support: Default/SDR12
[SD0] Support: HS/SDR25
[SD0] Support: Type-B Drv
[SD0] Support: 200mA current limit
[SD0] Switch to HS mode!
[SD0] Bus Width: 4
[SD0] Size: 1910 MB, Max.Speed: 50000 kHz, blklen(512), nblks(3911680), ro(0)
[SD0] Initialized
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] Bus Width: 4
[TST] 0x8000000 - 0x8020000 Erased
[SD0] <PASS> TC0: test single block write
[SD0] <PASS> TC1: test single block read
[SD0] <PASS> TC2: test multiple block write
[SD0] <PASS> TC3: test multiple block read
[SD0] <PASS> TC4: test multiple block interleave write-read
[TST] ----------------------------------------------
[TST] Report -  Desc. DMA R/W Test 
[TST] ----------------------------------------------
[TST] ----------------------------------------------
[TST] Test Result: TOTAL(1/1), PASS(1), FAIL(0) 
[TST] ----------------------------------------------
Desc. DMA Test pass!
[TST] ==============================================
[TST] BEGIN: 1/1, No Stop(0)
[TST] ----------------------------------------------
[TST] Mode    : 4
[TST] Clock   : 48000 kHz
[TST] BusWidth: 4 bits
[TST] BurstSz : 64 bytes
[TST] BlkAddr : 40000h
[TST] BlkSize : 512bytes
[TST] TstBlks : 256
[TST] AutoCMD : 12(0), 23(0)
[TST] ----------------------------------------------
[SD0] Bus Width: 1
[SD0] SET_CLK(260kHz): SCLK(255kHz) MODE(0) DDR(0) DIV(47) DS(0) RS(0)
[SD0] SD_SPEC(2) SD_SPEC3(1) SD_BUS_WIDTH=5
[SD0] SD_SECU(2) EX_SECU(0), CMD_SUPP(0): CMD23(0), CMD20(0)
[SD0] Support: Default/SDR12
[SD0] Support: HS/SDR25
[SD0] Support: Type-B Drv
[SD0] Support: 200mA current limit
[SD0] Switch to HS mode!
[SD0] Bus Width: 4
[SD0] Size: 1910 MB, Max.Speed: 50000 kHz, blklen(512), nblks(3911680), ro(0)
[SD0] Initialized
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] Bus Width: 4
[TST] 0x8000000 - 0x8020000 Erased
[SD0] <PASS> TC0: test single block write
[SD0] <PASS> TC1: test single block read
[SD0] <PASS> TC2: test multiple block write
[SD0] <PASS> TC3: test multiple block read
[SD0] <PASS> TC4: test multiple block interleave write-read
[TST] ----------------------------------------------
[TST] Report -  Enhanced DMA R/W Test 
[TST] ----------------------------------------------
[TST] ----------------------------------------------
[TST] Test Result: TOTAL(1/1), PASS(1), FAIL(0) 
[TST] ----------------------------------------------
[TST] ==============================================
[TST] BEGIN: 1/1, No Stop(0)
[TST] ----------------------------------------------
[TST] Mode    : 4
[TST] Clock   : 48000 kHz
[TST] BusWidth: 4 bits
[TST] BurstSz : 64 bytes
[TST] BlkAddr : 40000h
[TST] BlkSize : 512bytes
[TST] TstBlks : 256
[TST] AutoCMD : 12(0), 23(0)
[TST] ----------------------------------------------
[SD0] Bus Width: 1
[SD0] SET_CLK(260kHz): SCLK(255kHz) MODE(0) DDR(0) DIV(47) DS(0) RS(0)
[SD0] SD_SPEC(2) SD_SPEC3(1) SD_BUS_WIDTH=5
[SD0] SD_SECU(2) EX_SECU(0), CMD_SUPP(0): CMD23(0), CMD20(0)
[SD0] Support: Default/SDR12
[SD0] Support: HS/SDR25
[SD0] Support: Type-B Drv
[SD0] Support: 200mA current limit
[SD0] Switch to HS mode!
[SD0] Bus Width: 4
[SD0] Size: 1910 MB, Max.Speed: 50000 kHz, blklen(512), nblks(3911680), ro(0)
[SD0] Initialized
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] Bus Width: 4
[TST] 0x8000000 - 0x8020000 Erased
[SD0] <PASS> TC0: test single block write
[SD0] <PASS> TC1: test single block read
[SD0] <PASS> TC2: test multiple block write
[SD0] <PASS> TC3: test multiple block read
[SD0] <PASS> TC4: test multiple block interleave write-read
[TST] ----------------------------------------------
[TST] Report -  Enhanced DMA R/W Test 
[TST] ----------------------------------------------
[TST] ----------------------------------------------
[TST] Test Result: TOTAL(1/1), PASS(1), FAIL(0) 
[TST] ----------------------------------------------
Enhance DMA Test pass!
[TST] ==============================================
[TST] BEGIN: 1/1, No Stop(0)
[TST] ----------------------------------------------
[TST] Mode    : 2
[TST] Clock   : 48000 kHz
[TST] BusWidth: 4 bits
[TST] BurstSz : 64 bytes
[TST] BlkAddr : 40000h
[TST] BlkSize : 512bytes
[TST] TstBlks : 256
[TST] AutoCMD : 12(1), 23(0)
[TST] ----------------------------------------------
[SD0] Bus Width: 1
[SD0] SET_CLK(260kHz): SCLK(255kHz) MODE(0) DDR(0) DIV(47) DS(0) RS(0)
[SD0] SD_SPEC(2) SD_SPEC3(1) SD_BUS_WIDTH=5
[SD0] SD_SECU(2) EX_SECU(0), CMD_SUPP(0): CMD23(0), CMD20(0)
[SD0] Support: Default/SDR12
[SD0] Support: HS/SDR25
[SD0] Support: Type-B Drv
[SD0] Support: 200mA current limit
[SD0] Switch to HS mode!
[SD0] Bus Width: 4
[SD0] Size: 1910 MB, Max.Speed: 50000 kHz, blklen(512), nblks(3911680), ro(0)
[SD0] Initialized
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] Bus Width: 4
[TST] 0x8000000 - 0x8020000 Erased
[SD0] <PASS> TC0: test single block write
[SD0] <PASS> TC1: test single block read
[SD0] <PASS> TC2: test multiple block write
[SD0] <PASS> TC3: test multiple block read
[SD0] <PASS> TC4: test multiple block interleave write-read
[TST] ----------------------------------------------
[TST] Report -  Auto CMD12 Test 
[TST] ----------------------------------------------
[TST] ----------------------------------------------
[TST] Test Result: TOTAL(1/1), PASS(1), FAIL(0) 
[TST] ----------------------------------------------
[TST] ==============================================
[TST] BEGIN: 1/1, No Stop(0)
[TST] ----------------------------------------------
[TST] Mode    : 3
[TST] Clock   : 48000 kHz
[TST] BusWidth: 4 bits
[TST] BurstSz : 64 bytes
[TST] BlkAddr : 40000h
[TST] BlkSize : 512bytes
[TST] TstBlks : 256
[TST] AutoCMD : 12(1), 23(0)
[TST] ----------------------------------------------
[SD0] Bus Width: 1
[SD0] SET_CLK(260kHz): SCLK(255kHz) MODE(0) DDR(0) DIV(47) DS(0) RS(0)
[SD0] SD_SPEC(2) SD_SPEC3(1) SD_BUS_WIDTH=5
[SD0] SD_SECU(2) EX_SECU(0), CMD_SUPP(0): CMD23(0), CMD20(0)
[SD0] Support: Default/SDR12
[SD0] Support: HS/SDR25
[SD0] Support: Type-B Drv
[SD0] Support: 200mA current limit
[SD0] Switch to HS mode!
[SD0] Bus Width: 4
[SD0] Size: 1910 MB, Max.Speed: 50000 kHz, blklen(512), nblks(3911680), ro(0)
[SD0] Initialized
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] Bus Width: 4
[TST] 0x8000000 - 0x8020000 Erased
[SD0] <PASS> TC0: test single block write
[SD0] <PASS> TC1: test single block read
[SD0] <PASS> TC2: test multiple block write
[SD0] <PASS> TC3: test multiple block read
[SD0] <PASS> TC4: test multiple block interleave write-read
[TST] ----------------------------------------------
[TST] Report -  Auto CMD12 Test 
[TST] ----------------------------------------------
[TST] ----------------------------------------------
[TST] Test Result: TOTAL(1/1), PASS(1), FAIL(0) 
[TST] ----------------------------------------------
[TST] ==============================================
[TST] BEGIN: 1/1, No Stop(0)
[TST] ----------------------------------------------
[TST] Mode    : 4
[TST] Clock   : 48000 kHz
[TST] BusWidth: 4 bits
[TST] BurstSz : 64 bytes
[TST] BlkAddr : 40000h
[TST] BlkSize : 512bytes
[TST] TstBlks : 256
[TST] AutoCMD : 12(1), 23(0)
[TST] ----------------------------------------------
[SD0] Bus Width: 1
[SD0] SET_CLK(260kHz): SCLK(255kHz) MODE(0) DDR(0) DIV(47) DS(0) RS(0)
[SD0] SD_SPEC(2) SD_SPEC3(1) SD_BUS_WIDTH=5
[SD0] SD_SECU(2) EX_SECU(0), CMD_SUPP(0): CMD23(0), CMD20(0)
[SD0] Support: Default/SDR12
[SD0] Support: HS/SDR25
[SD0] Support: Type-B Drv
[SD0] Support: 200mA current limit
[SD0] Switch to HS mode!
[SD0] Bus Width: 4
[SD0] Size: 1910 MB, Max.Speed: 50000 kHz, blklen(512), nblks(3911680), ro(0)
[SD0] Initialized
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] SET_CLK(48000kHz): SCLK(48000kHz) MODE(1) DDR(0) DIV(0) DS(0) RS(0)
[SD0] Bus Width: 4
[TST] 0x8000000 - 0x8020000 Erased
[SD0] <PASS> TC0: test single block write
[SD0] <PASS> TC1: test single block read
[SD0] <PASS> TC2: test multiple block write
[SD0] <PASS> TC3: test multiple block read
[SD0] <PASS> TC4: test multiple block interleave write-read
[TST] ----------------------------------------------
[TST] Report -  Auto CMD12 Test 
[TST] ----------------------------------------------
[TST] ----------------------------------------------
[TST] Test Result: TOTAL(1/1), PASS(1), FAIL(0) 
[TST] ----------------------------------------------
Auto Command 12 Test pass!
[SDMMC] Stress test successfully
RT6352 # 